TSA0801IFT ,8-BIT, 40MSPS, 40MW A/D CONVERTERBLOCK DIAGRAM VREFP+2.5VGNDAVINReferencestage stage stageINCMIPOLcircuit 1 2 nVINBVRE ..
TSA1001CF ,10-BIT, 25MSPS, 35MW A/D CONVERTERBLOCK DIAGRAM VREFP+2.5VGNDAVINReferencestage stage stageINCM IPOLcircuit 1 2 nVINBVRE ..
TSA1001CFT ,10-BIT, 25MSPS, 35MW A/D CONVERTERNCD9 (MSB)DRORVCCBVCCBGNDBGNDBVCCBGNDBNCDGNDNC NCOEBDGNDDFSBCLKAVCCDGNDAVCCDVCCAGNDDV ..
TSA1001IF ,10-BIT, 25MSPS, 35MW A/D CONVERTERABSOLUTE MAXIMUM RATINGS Symbol Parameter Values Unit1)AVCC 0 to 3.3 VAnalog Supply voltage 1)DVC ..
TSA1001IFT ,10-BIT, 25MSPS, 35MW A/D CONVERTERapplications, the26AVCC D711TSA1001 only dissipates 35mW at 25Msps. When25AVCC 12 D8running at lowe ..
TSA1002CFT ,10-BIT, 50MSPS, 50MW A/D CONVERTERBLOCK DIAGRAM VREFP+2.5VGNDAVINReferencestage stageINCM stageIPOLcircuit 1 2 nVINBVR ..
UAA4009 ,Remote Control Receiver£77
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UAA4009 ,Remote Control ReceiverGENERAL DESCRIPTION
PPM DEMODULATION
The receiver operates on a timescale fixed by an in-
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UAA4713DP ,MOTION DETECTOR INTERFACEapplications.The device can be usedprogrammable timer will start and switch a lampin a wide range o ..
UAA4713FP ,MOTION DETECTOR INTERFACEABSOLUTE MAXIMUM RATINGSSymbol Parameter Test Conditions UnitI7 AC Supply Current 60 mAI7 Peak Curr ..
UAF1780 ,DUAL 2A LOW DROP OUT INTELLIGENT POWER SWITCHCO SGS-THOMSON
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UAF41 , DIODE-PENTODE
TSA0801IFT
8-BIT, 40MSPS, 40MW A/D CONVERTER
8-bit A/D converter in deep submicron CMOS technology� Single supply voltage: 2.5V� Input range: 2Vpp differential� 40Msps sampling frequency Ultra low power consumption: 40mW @
40Msps (10mW @ 5Msps)� ENOB=7.97 @ 40Msps, Fin=5MHz� SFDR typically up to 68dB @ 40Msps,
Fin=5MHz� Built-in reference voltage with external bias
capability Pinout compatibility with TSA1001, TSA1002
and TSA1201.
DESCRIPTIONThe TSA0801 is an 8-bit, 40MHz sampling fre-
quency Analog to Digital converter using a deep
submicron CMOS technology combining high per-
formances and very low power consumption.
The TSA0801 is based on a pipeline structure and
digital error correction to provide excellent static
linearity and go beyond 7.9 effective bits at
Fs=40Msps, and Fin=5MHz.
A voltage reference is integrated in the circuit to
simplify the design and minimize external compo-
nents. It is nevertheless possible to use the circuit
with an external reference.
Differential or single-ended analog inputs can be
applied to the converter. A tri-state capability is
available on the outputs. The output data can be
coded into two different formats. A Data Ready
signal is raised as the data is valid on the output
and can be used for synchronization purposes.
The TSA0801 is available in commercial (0 to
+70°C) and extended (-40 to +85°C) temperature
range, in a small 48 pins TQFP package.
APPLICATIONS Hand-held instrumentation� Medical imaging and Ultrasound� Camcorders Computer scanners� Digital communication
ORDER CODE
PIN CONNECTIONS (top view)
PACKAGE
TSA08018-BIT, 40MSPS, 40mW A/D CONVERTER
TSA0801
ABSOLUTE MAXIMUM RATINGS
OPERATING CONDITIONS Condition VRefP-VRefM>0.3V
BLOCK DIAGRAM All voltages values, except differential voltage, are with respect to network ground terminal. The magnitude of input and output voltages
must never exceed -0.3V or VCC+0V
TSA0801
PIN CONNECTIONS (top view)
PIN DESCRIPTION
TSA0801
ELECTRICAL CHARACTERISTICSAVCC = DVCC = VCCB = 2.5V, Fs= 40Msps,Fin=1MHz, Vin@ -1.0dBFS, VREFM = 0V
Tamb = 25°C (unless otherwise specified)
TIMING CHARACTERISTICS
TIMING DIAGRAM
TSA0801
CONDITIONSAVCC = DVCC = VCCB = 2.5V, Fs= 40Msps,Fin= 1MHz, Vin@ -1.0dBFS, VREFM= 0V
Tamb = 25°C (unless otherwise specified)
ANALOG INPUTS
REFERENCE VOLTAGE See parameters definition for more information Not fully tested over the temperature range. Guaranteed by sampling.
TSA0801
CONDITIONSAVCC = DVCC = VCCB = 2.5V, Fs= 40Msps, Fin= 1MHz, Vin@ -1.0dBFS, VREFP=1V, VREFM= 0V
Tamb = 25°C (unless otherwise specified)
POWER CONSUMPTION
DIGITAL INPUTS AND OUTPUTS
ACCURACY Rpol= 18KΩ. Equivalent load: Rload= 470Ω and Cload= 6pF Not fully tested over the temperature range. Guaranteed by sampling.
TSA0801
CONDITIONSAVCC = DVCC = 2.5V, Fs= 40Msps, Vin@ -1.0dBFS, VREFP=1V, VREFM= 0V
Tamb = 25°C (unless otherwise specified)
DYNAMIC CHARACTERISTICS Rpol= 18KΩ. Equivalent load: Rload= 470Ω and Cload= 6pF Tmin= -40°C to Tmax= 85°C. Not fully tested over the temperature range. Guaranteed by sampling.
TSA0801
DEFINITIONS OF SPECIFIED PARAMETERS
STATIC PARAMETERSStatic measurements are performed through
method of histograms on a 2MHz input signal,
sampled at 40Msps, which is high enough to fully
characterize the test frequency response. The
input level is +1dBFS to saturate the signal.
Differential Non Linearity (DNL)The average deviation of any output code width
from the ideal code width of 1LSB.
Integral Non linearity (INL)An ideal converter presents a transfer function as
being the straight line from the starting code to the
ending code. The INL is the deviation for each
transition from this ideal curve.
DYNAMIC PARAMETERSDynamic measurements are performed by
spectral analysis, applied to an input sine wave of
various frequencies and sampled at 40Msps.
Spurious Free Dynamic Range (SFDR)The ratio between the amplitude of fundamental
tone (signal power) and the power of the worst
spurious signal (not always an harmonic) over the
full Nyquist band. It is expressed in dBc.
Total Harmonic Distortion (THD)The ratio of the rms sum of the first five harmonic
distortion components to the rms value of the
fundamental line. It is expressed in dB.
Signal to Noise Ratio (SNR)The ratio of the rms value of the fundamental
component to the rms sum of all other spectral
components in the Nyquist band (fs /2) excluding
DC, fundamental and the first five harmonics.
SNR is reported in dB.
Signal to Noise and Distortion Ratio (SINAD)Similar ratio as for SNR but including the harmonic
distortion components in the noise figure (not DC
signal). It is expressed in dB.
From the SINAD, the Effective Number of Bits
(ENOB) can easily be deduced using the formula:
SINAD= 6.02 × ENOB + 1.76 dB.
When the applied signal is not Full Scale (FS), but
has an A0 amplitude, the SINAD expression
becomes:
SINAD= 6.02 × ENOB + 1.76 dB + 20 log (2A0/FS)
The ENOB is expressed in bits.
Analog Input BandwidthThe maximum analog input frequency at which the
spectral response of a full power signal is reduced
by 3dB. Higher values can be achieved with
smaller input levels.
Effective Resolution Bandwidth (ERB)The band of input signal frequencies that the ADC
is intended to convert without loosing linearity i.e.
the maximum analog input frequency at which the
SINAD is decreased by 3dB or the ENOB by 1/2
bit.
Pipeline delayDelay between the initial sample of the analog in-
put and the availability of the corresponding digital
data output, on the output bus. Also called data la-
tency. It is expressed as a number of clock cycles.
TSA0801
Static parameter: Integral Non LinearityFs=40MSPS; Fin=1MHz; Icca=11mA; N=65536pts
Static parameter: Differential Non LinearityFs=40MSPS; Fin=1MHz; Icca=11mA; N=65536pts
Linearity vs. FsFin=5MHz; Rpol adjustment
Distortion vs. FsFin=5MHz; Rpol adjustment
TSA0801
Linearity vs. FsFin=15MHz; Rpol adjustment
Linearity vs. Fin Fs=40MSPS; Icca=11mA
Linearity vs. TemperatureFs=40MSPS; Icca=11mA; Fin=5MHz
Distortion vs. FsFin=15MHz; Rpol adjustment
Distortion vs. FinFs=40MSPS; Icca=11mA
Distortion vs. TemperatureFs=40MSPS; Icca=11mA; Fin=5MHz;
TSA0801
Power spectrum Fs=40MSPS - Icca=11mA - Fin=1MHz
Power spectrumFs=40MSPS - Icca=11mA - Fin=10MHz
Power spectrumFs=40MHz - Icca=11mA - Fin=50MSPS