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TS556IDSTN/a2042avaiLOW POWER DUAL CMOS TIMER
TS556IDTSTN/a15000avaiLOW POWER DUAL CMOS TIMER
TS556IN ST N/a20000avaiLOW POWER DUAL CMOS TIMER
TS556CDTSTMN/a1255avaiLOW POWER DUAL CMOS TIMER
TS556CDSTN/a891avaiLOW POWER DUAL CMOS TIMER
TS556CNSTMN/a1210avaiLOW POWER DUAL CMOS TIMER


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TS556CD-TS556CDT-TS556CN-TS556ID-TS556IDT-TS556IN
LOW POWER DUAL CMOS TIMER
TS556C,I,M
LOW POWER DUAL CMOS TIMERS
October 1997 VERY LOW POWER CONSUMPTION :. 100μA typ at VCC = 5V. HIGH MAXIMUM ASTABLE FREQUENCY
2.7MHz. PIN-TO-PIN AND FUNCTIONALLY
COMPATIBLE WITH BIPOLAR NE555. VOLTAGE RANGE : +2V to +18V. HIGH OUTPUT CURRENT CAPABILITY. SUPPLY CURRENT SPIKES REDUCED
DURING OUTPUT TRANSITIONS . HIGH INPUT IMPEDANCE : 1012 Ω. OUTPUT COMPATIBLE WITH TTL,CMOS
AND LOGIC MOS
PIN CONNECTIONS (top view)
ORDER CODES
DESCRIPTION

The TS556 is a dual CMOS timer which offers very
low consumption (Icc(TYP) TS556 = 200μA
Icc(TYP) NE556 = 6mA) and high frequency
(f(max.) TS556 = 2.7MHz - f(max.) NE556 = 0.1 MHz)
Thus, either in Monostable or Astable mode, tim-
ing remains very accurate.
The TS556 provides reduced supply current
spikes during output transitions, which enables
the use of lower decoupling capacitors compared
to those required by bipolar NE556.
Timing capacitors can also be minimized due to
high input impedance (1012 Ω).
1/11
LOW � Level Voltage ≤ Min voltage specified
HIGH
� Level Voltage ≥ Max voltage specified � Irrelevant
ABSOLUTE MAXIMUM RATINGS
THERMAL CHARACTERISTICS
BLOCK DIAGRAM
TS556C,I,M

2/11
SCHEMATIC DIAGRAM (1/2 TS556)
TS556C,I,M

3/11
STATIC ELECTRICAL CHARACTERISTICS
VCC = +2V, Tamb = +25o C, Reset to VCC (unless otherwise specified)
OPERATING CONDITIONS
TS556C,I,M

4/11
STATIC ELECTRICAL CHARACTERISTICS (continued)
VCC = +5V, Tamb = +25o C, Reset to VCC (unless otherwise specified)
TS556C,I,M

5/11
STATIC ELECTRICAL CHARACTERISTICS (continued)
VCC = +12V, Tamb = +25o C, Reset to VCC (unless otherwise specified)
TS556C,I,M

6/11
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