TPIC6A259DW ,8-Bit Addressable Latchfeatures an independentPGND 5 20 PGNDchopping current-limiting circuit to preventPGND PGND6 19damag ..
TPIC6A595DW ,8-Bit Shift Registerfeatures an independent 3 22G Vchopping current-limiting circuit to prevent 4 21CCPGND PGNDdamage i ..
TPIC6A595NE ,8-Bit Shift Registermaximum ratings over recommended operating case temperature range (unless†otherwise noted)Logic sup ..
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TPIC6B259DWR ,8-Bit Addressable Latch TPIC6B259 POWER LOGIC 8-BIT ADDRESSABLE LATCH SLIS030 – APRIL 1994 – REVISED JULY 1995* Low r ...5 ..
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TS3USB3200RSVR ,USB 2.0 High-Speed and Mobile High-Definition Link Switch w/ ID Select and Flexible Power Control 16-UQFN -40 to 85Featurescontrol. These configurations allow the systemdesigner to use a common USB or Mico-USB– Fle ..
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TS3V330DGVR ,Quad SPDT Wide Bandwidth Video Switch with Low On-State ResistanceFEATURESD, DBQ, DGV, OR PW PACKAGE• Low Differential Gain and Phase (D = 0.82%,G (TOP VIEW)D = 0.1 ..
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TPIC6A259DW
8-Bit Addressable Latch
50-V Switching Capability Four Distinct Function Modes Low Power Consumption
descriptionThis power logic 8-bit addressable latch controls
open-drain DMOS-transistor outputs and is
designed for general-purpose storage appli-
cations in digital systems. Specific uses include
working registers, serial-holding registers, and
decoders or demultiplexers. This is a multi-
functional device capable of operating as eight
addressable latches or an 8-line demultiplexer
with active-low DMOS outputs. Each open-drain
DMOS transistor features an independent
chopping current-limiting circuit to prevent
damage in the case of a short circuit.
Four distinct modes of operation are selectable by
controlling the clear (CLR) and enable (G) inputs
as enumerated in the function table. In the
addressable-latch mode, data at the data-in (D)
terminal is written into the addressed latch. The
addressed DMOS-transistor output inverts the
data input with all unaddressed DMOS-transistor
outputs remaining in their previous states. In the
memory mode, all DMOS-transistor outputs
remain in their previous states and are unaffected
by the data or address inputs. To eliminate the
possibility of entering erroneous data in the latch,
enable G should be held high (inactive) while the
address lines are changing. In the 8-line
demultiplexing mode, the addressed output is
inverted with respect to the D input and all other
outputs are high. In the clear mode, all outputs are
high and unaffected by the address and data
inputs.
Separate power ground (PGND) and logic ground
(LGND) terminals are provided to facilitate
maximum system flexibility. All PGND terminals
are internally connected, and each PGND
terminal must be externally connected to the
power system ground in order to minimize
parasitic impedance. A single-point connection
between LGND and PGND must be made
externally in a manner that reduces crosstalk
between the logic and load circuits.
FUNCTION TABLE
LATCH SELECTION TABLELGND
PGND
PGND
DRAIN4
DRAIN5
VCC
PGND
PGND
CLR
DRAIN7
DRAIN6
DRAIN2
DRAIN3
LGND
PGND
PGND
PGND
PGND
DRAIN4
DRAIN5
DRAIN1
DRAIN0
VCC
PGND
PGND
PGND
PGND
CLR
DRAIN7
DRAIN6
DW PACKAGE
(TOP VIEW)
