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TPD7202F
POWER MOSFET GATE DRIVER FOR H BRIDGE
TOSHIBA TPD7202F
TENTATIVE TOSHIBA INTELLIGENT POWER DEVICE
SILICON MONOLITHIC POWER MOS INTEGRATED CIRCUIT
TPD7202F
POWER MOSFET GATE DRIVER FOR H BRIDGE
TPD7202F is a power MOSFET Gate driver for H-bridge
circuit using charge pump system. Because this IC contains
a charge pump circuit for high-side drive, it allows you to
configure H-bridge circuit.
FEATURES
It Power MOSFET Gate Driver for H-bridge circuit
o Built-in power MOSFET protection and diagnosis functions:
Overvoltage and low-voltage protection
SSOP24-P-300-1.00B
o Built-in a charge pump circuit.
Weight : 0.299 (typ.)
0 Package : SSOP-24 (300 mil) with embossed-tape packing
PIN ASSIGNMENT MARKING
(TOP VIEW) Toshiba Trademark
Coscl 0 Eslmt onnrrfinrvnnrunn
R 2 23 M /
“CE 3 + G'' |:| -- Lot code
Ihl4 [E El OUT1
NOE EM- T P D 7 2 0 2 F --- Product no.
|N1E EOUTZ
ME Em. LILILILILIIJLILILILILILI
N.C. IZ EN-C- Lot code naming system
INBE EOUT3 UDUUU
FAULTE EOUTII Le LTOShiba house no.
Manufactured week (52 weeks or 53
SGND E Cs] PGND weeks indicating system starting from
CPI E E NC the first Thursday of January)
CP2 12 EVDD Manufactured year (last two digits of
the year)
Because this product uses MOS structure, must take special care with electrostatic when
handling.
980910EBA2
O TOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in general can
malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing
TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss
of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified
operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions set forth in the
TOSHIBA Semiconductor Reliability Handbook.
0 The products described in this document are subject to the foreign exchange and foreign trade laws.
0 The information contained herein is presented only as a guide for the apflications of our products. No responsibility is assumed by TOSHIBA
CORPORATION for any infringements of intellectual property or other rights o the third parties which may result from its use. No license is granted
h implication or otherwise Under any intellectual property or other rights of TOSHIBA CORPORATION or others.
0 T e information contained herein is subject to change without notice.
2000-03-02 1/17
TOSHIBA
TENTATIVE
BLOCK DIAGRAM /APPLICATION CIRCUIT
TPD7202F
Reverse connection protection
u. > +
t, E w, 'i,'
g 0 Ct ''ss I
m o . LL
Fl '" ol g
tt 1 2 11 12 24
VDD Cosc Rosc CPiY "i' CPVY
OSC Charge pump
r-ls-u power supply l-
Overvoltage
protection Circuit
Low voltage -
protection circuit
(Note) :
Logic Circuit
(*1) 100 kg
D -a'rs--,
" r-Ne
M + (*2) n "C/ht'
100 k 100 k
23 'N. O M +
L OUT2 ( 1)
2 -NV',
f M - (*2)
'ity' AVAVA' O M -
:1 ourd, (*1) - -
f 'sly' NNN . i: =1
: Optimum conditions depend on switching loss, EMI, etc. of external MOSFET.
: SBD VF = 0.5Vmax (Recommended .' CRSOB)
This is needed when the M+ or M - pin is biased to the negative side by more than 0.5 V.
: This is a laminated ceramic capacitor.
: High-speed diode trr = 100 ns max (Recommended : CRH01)
When selecting external parts, please read "Method for selecting external parts"
described later.
2000-03-02 2/17
TOSHIBA
TENTATIVE
PIN DESCRIPTION
TPD7202F
PIN No. SYMBOL PIN DESCRIPTION
1 COSC This pin sets the oscillation frequency for. charge pump drive.
Connect a 1500 pF (recommended) capacitor.
2 ROSC This pin sets the oscillation fre.quency/or charge pump drive.
Connect a 100 k0 (recommended) resistor.
3 IN4 Input pin: it controls the power MOS connected to OUT4 (low side of M-).
Built-in pull-down resistor (100 k0 typ.).
4 NC. -
5 IN1 Input pin: it controls the power MOS connected to OUT1 (high side of M +).
Built-in pull-down resistor (100 k0 typ.)
6 lN2 Input pin: it controls the power MOS connected to OUT2 (high side of M -).
Built-in pull-down resistor (100 kfl typ.)
7 N.C. -
8 Ibl3 Input pin: it controls the power MOS connected to OUT3 (low side of M+).
Built-in pull-down resistor (100 k0 typ.)
9 FAULT Diagnosis output pin: when Iow-voltage 6V (typ.) or overvoltage 22V (typ.) is
detected, output "H". Circuit configuration is N-ch open drain.
10 SGND Signal block GND pin
11 CPI Capacitor pin for charge pump.
Connect a 0.47 pF (recommended) laminated ceramic capacitor.
12 CP2 Capacitor pin for charge pump.
Connect a 0.47 pF (recommended) laminated ceramic capacitor.
13 VDD Power supply pin: when low voltage (6V typ.) or overvoltage (22V typ.) is
detected, all outputs are shut down.
14 N.C. -
15 PGND Power block GND pin
16 OUT4 Drives the power MOSFET connected to the low side of M -.
17 OUT3 Drives the power MOSFET connected to the low side of M +.
18 NC. -
19 NC. -
20 OUT2 Drives the power MOSFET connected to the high side of M -.
21 M - Output pin
22 OUT1 Drives the power MOSFET connected to the high side of M +.
23 M + Output pin
Final stage capacitor for the charge pump.
24 CPV Connect IPF (recommended) laminated ceramic capacitor and 10 pF
(recommended) aluminum electrolytic capacitor in parallel.
2000-03-02 3/17
TOSHIBA
TPD7202F
TENTATIVE
TRUTH TABLE
INPUT OUTPUT
lN1 Ihl2 IN3 IN4 OUT1 OUT2 OUT3 OUT4 REMARKS
L L L L L L L L Stop mode
H L L H H L L H Forward mode
L H H L L H H L Reverse mode
L L H H L L H H Brake mode
H L H L L L L L High side/Low side arm shorting mode(*)
L H L H L L L L High side/Low side arm shorting mode(*)
(FAULT is kept low.)
When undervoltage (6V typ.) or overvoltage (22V typ.) is detected, all
outputs are pulled low regardless of input signals. At this time, FAULT
output goes high (open-drain, high-impedance).
MAXIMUM RATING (Ta = 25°C)
High side/Low side arm shorting mode is disabled by the internal logic.
CHARACTERISTIC SYMBOL RATING UNIT REMARKS
Power Supply Voltage VDD -0.5--30 V
Output Current SOURCE A Pulse width s 10ps
'SINK 1
Input Voltage VIN -0.r-7.0 V
FAULT Pin Voltage VFAULT 30 V
M +, M - Pin Negative M + (-) Negétlve voltage that can he
Volta e M- (-) -0.5 V applied to M+ and M- pins
g (Reference to SGND pin)
Negative voltage that can be
PGND Pin Negative Voltage PGND(-) -0.5 V applied to PGND pin
(Reference to SGND pin)
Fault Pin Current IFAULT 5 mA
. . . 0.8
Power Dissipation PD 1.5 (Note) W
Operating Temperature Topr -40--125 "C
Storage Temperature Tstg -40--150 ''C
THERMAL RESISTANCE
CHARACTERISTIC SYMBOL RATING UNIT
Junction to Ambient Thermal 156.3 C)
Resistance Rth (j-a) 83.4 (Note) C/W
(Note) : When a device mounted on 60mm x 60mm x 1.6t glass epoxy PCB.
2000-03-02 4/17
TOSHIBA TPD7202F
TENTATIVE
ELECTRICAL CHARACTERISTICS (Unless otherwise specified, Ta = -40--125''C)
CHARACTERISTIC SYMBOL CIR- CONDITION MIN. TYP. MAX. UNIT REMARKS
Operating Supply
V - - 7 13.5 18 V
Voltage DD
IDD(1) 1 VDD = 13.5V - - 10 Oscillation circuit stops
Supply Current VDD = 13.5 V, mA When oscillation circuit
IDD (2) 2 l/INV-VIN, - - 100 is operating f = 20
= 0V kHz, mean current
VIH 3.5 - - 1N1-IN4 high-level
In ut Volta e 2 VDD = 7--18V, V input voltage
p g Io = 0A llN1-IN4 Iow-level
VIL - - 1.5 .
input voltage
VDD = 7--18V,
IIH VIN = 5V, - - 1 mA
I t c t 2 Ity = 0A 1N1-IN4 in ut current
npu urren VDD = T-18V, p
IIL VIN = ov, -1o - 10 PA
Io = 0A
VDD = 13.5 V: V OUT1 pin voltage
v v - 5v CPV - v .
OH IN - ' -2 CPV (reference to M + pin)
High side lo = 0A OUT2 pin voltage .
VDD = 13.5 V, (reference to M - pin)
VOL VIN = 0V, - - 0.1 VCPV denotes CPV pin
Output 2 IO = DA V voltage
Voltage VDD = 13.5V OUT3 pin voltage
VOH VIN = SV,, 11.5 - 13.5 (reference to PGND
Low side IO = 0A pin) .
VDD = 13.5 V, OUT4 pm voltage
VOL VIN = 0V, - - 0.1 (reference to PGND
Io = 0A pin)
CPV pin voltage
Charge Pump vcpv 2 VDD = 13.5v 23.5 - 34 v (reference to SGND
Voltage .
Clamp voltage
between OUT1 and
High side VIN = SV, 14 - 20 M+ pins
Acti e lo = 10 mA Clamp voltage
IV between OUT2 and
Clamp VCLAMP - V M- pins
Voltage OUT3 and OUT4 pins
. VIN = 5V, clamp voltage
- 18 -
Low side lo = 10 mA (reference to PGND
2000-03-02 5/17
TOSHIBA TPD7202F
TENTATIVE
CHARACTERISTIC SYMBOL CIR- CONDITION MIN. TYP. MAX. UNIT REMARKS
VDD = 13.5 V,
R V = 5V, - 7 10
SOURCE I (l 0 5A OUT1-OUT4 output
Output Resistance 2 'f, _'13 5 V fl resistance
RSINK 1t1.Cili, ' - 4 5 10 pulse width s 10ps
IO = -0.5A
Low- Detection VSD (L) 5.5 6 6.5 Lowvoltage detectIor-I
Voltage 3 V voltage and hysteresis
. . - (VDD voltage
Protection Hysteresis AVSD (L) - 0.5 - detected)
Over- Detection VSD(H) 20 22 24 Overvoltage fettctio.n
Voltage 3 V voltage and hysteresis
. . - (VDD voltage
Protection Hysteresis AVSD (H) - 2 - detected)
Turn-on
delay td (ON) - - 4
Turn-on - -- - -
Swithcing time tON 4 gm 170327“ F 6 OUT1-OUT4 switching
Time Turn-off OUT - . ’u ' ps time
cl_elay td (OFF) RG = 47 n - - 4
T - ff
ti”r;2° tOFF - - 6
- fOSC calculation
Oscillating fosc 2 ngDc_-710:38k\6 20 kHz formula
Frequency COSC = 1500 pFl fOSC = 3/{Cosc (ROSC
+ 2 k)} (Hz)
FAULT Pin FAULT pin Iow-level
Voltage VFAULT 2 IFAULT - 1 mA - - 0.8 V voltage (open-drain)
Time from low voltage
FAULT Delay tON 'l/td] . ','d, kn - 1 - /overvoltage detection
Time 3 (External power ps 'lf risT’coratIon to
tOFF supply) - 1 - AU output
inversion
2000-03-02 6/17
TOSHIBA
TENTATIVE
TESTING CIRCUIT 1 IDD(1)
i 11.y \1/ l.?.,) Ci) (i)), (ii)
VDD Cosc Rosc CP1 CP2 CPV
9 PII OUT1 Q
G lN2 M+ Cii
9 ma TPD7202F M-
OINA our3®
eFAULT
TESTING CIRCUIT 2 IDD (2), VIH, VIL, IIH, IIL, VOH, VOL, VCPV, VFAULT
N100k0
j,,rii'zi-i! (l,)"
V V 'sLli
VDD Cosc Rosc CPI
TPD7202F
TPD7202F
2000-03-02 7/17
TOSHIBA TPD7202F
TENTATIVE
TESTING CIRCUIT 3 VSD(L), AV5D(L), VSD(H): AVSD (H), FAULT delay time tON, tOFF
r\/\/\/\/\
1l.y1,.Ut.2..,it1...1i1,1..y'syy
VDD Cosc Rosc CP1 CP2 CPV
9 INI OUT1 a
G INZ M+ Q
OUT2 "ig'
9 |N3 TPD7202F M-
Ci? INA 0UT3 C/i
OUT4 Ciis2
9 FAULT SGND PGND
fi), Kh
V=5Vl oVFAULT I
low-voltage low-voltage Overvoltage Overvoltage
detection restoration detection restoration
VFAU LT waveform (50%)
tow tOFF tON tOFF
2000-03-02 8/17
TOSHIBA TPD7202F
TENTATIVE
TESTING CIRCUIT 4 td (ON), toN, td (OFF), tOFF
l VDD = 13.5V
A A prh CTs
q; IJ...) 'sd..) 'x1s..1.) 'st.?) 's2d1)
VDD COSC ROSC CPI CP2 CPV
TPD7202F
SGND PGND
ATh ATA
10 'ji''
5 V ....................
Input waveform
(50%) ............... v'""''''"'""'"""'''""'''"'''"""'''""'''"'"'""'''""'''". ..............................
VIN i g
....i................................................... ......
Output waveform
gtd (ON); . td (OFF) i
w-i. i i
_ tON ' ' tOFF '
2000-03-02 9/17
TOSHIBA
TPD7202F
TENTATIVE
IDD(1) - Ta
VDD =13.5V
VIN1~a = 0V
SUPPLY CURRENT |DD(1) (mA)
- 80 0 80 160
AMBIENT TEMPERATURE Ta (°C)
Vth ''L''-9''H" - VDD
Ta = 25°C
INPUT THRESHOLD VOLTAGE ”L" —>"H"
Vth (V)
0 5 10 15 20
POWER SUPPLY VOLTAGE VDD (V)
Vth ''L''-9''H'' - Ta
VDD = 13.5 V
INPUT THRESHOLD VOLTAGE ”L" —>"H”
Vth (V)
- 80 0 80 160
AMBIENT TEMPERATURE Ta (°C)
INPUT THRESHOLD VOLTAGE H —) L SUPPLY CURRENT 'DD(1) (mA)
INPUT THRESHOLD VOLTAGE "H" —)"L"
Vth (V)
Vth (V)
IDD(1) - Ta
VDD = 13.5V
VIN1 = 5V
VIN2--4 = 0V
-80 0 80 160
AMBIENT TEMPERATURE Ta (°C)
Vth ''H''-y''L" - VDD
Ta = 25°C
0 5 10 15 20
POWER SUPPLY VOLTAGE VDD (V)
Vth ''H''-y''L" - Ta
VDD =13.5V
- 80 O 80 160
AMBIENT TEMPERATURE Ta (°C)
2000-03-02 10/17
TOSHIBA
TENTATIVE
IIH (,uA)
INPUT CURRENT
OUTPUT DROP VOLTAGE VDROP (V)
OUTPUT DROP VOLTAGE vDRop (V)
IIH - Ta
VDD =13.5V
VIN = SV
- 80 0 80 160
AMBIENT TEMPERATURE Ta (°C)
VDROP - POWER SUPPLY VOLTAGE
Ta = 25°C, lo = 0A
(Note) :
The output drop voltage refers to a drop
voltage from the power supply voltage
when OUT1-OUT4 output is high.
OUT1 and OUT2 are drop voltages from the
3 CPV voltage. OUT3 and OUT4 are drop
voltages from the VDD voltage.
1 _,.-.---
0 5 10 15 20
POWER SUPPLY VOLTAGE VDD/chv (v)
VDROP - Ta
5 VDD = 13.5 v
Io = 0A
(Note) :
4 The output drop voltage refers to a drop
voltage from the power supply voltage
when OUT1-OUT4 output is high.
OUT1 and OUT2 are drop voltages from
3 the CPV voltage. OUT3 and OUT4 are drop
voltages from the VDD voltage.
- 80 0 80 160
AMBIENT TEMPERATURE Ta (°C)
INPUT CURRENT
OUTPUT VOLTAGE VOL (V)
OUTPUT VOLTAGE VOL (V)
TPD7202F
IIL - Ta
-80 0 80 160
AMBIENT TEMPERATURE Ta (°C)
VOL - POWER SUPPLY VOLTAGE
Ta = 25°C
VIN = 0 V
Io = 0A
0 5 10 15 20
POWER SUPPLY VOLTAGE VDD/VCPV (V)
VOL - Ta
-80 0 80 160
AMBIENT TEMPERATURE Ta (°C)
2000-03-02 11/17
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TOSHIBA TPD7202F
TENTATIVE
fosc - Ta VFAULT - Tj
25 1.25
20 1 I
8 "ii" ",--"
t 15 g 0.75 -
cvis:z, L-, "-""
o fl w..,--""
tl 10 2
u. E 0.5 /
g 5 l 0.25
[i, Rosc = 100 km IFAULT = 5 mA
Cosc = 1500 M f = 20 kHz
-50 0 50 100 150 -40 -20 0 20 40 60 80 100 120 140
AMBIENT TEMPERATURE Ta (°C) Tj (°C)
m 'ss.
'fi 0.4
-40 40 120
AMBIENT TEMPERATURE Ta (°C)
2000-03-02 14/17
TOSHIBA
TPD7202F
TENTATIVE
Method for selecting external parts
PIN RECOMMENDED VALUE/
No. PIN NAME TYPE RECOMMENDED PRODUCT DESCRIPTION
1 COSC Capacitor 1500 pF (ceramic) Sets charge pump's oscillation frequency.
2 ROSC Resistor 100 k0 Sets charge pump's oscillation frequency.
Capacitor for the charge pump. Greater
11 CP1 Capacitor 0.47 pF this capacitance larger the charging
12 CP2 (laminated ceramic) current to the capacitor, so there is a
greater loss in the IC.
IPF (laminated ceramic) Greater this capacitance, larger the charge
. and 10pF (aluminum pump (CEV pin) s current supply capacity,
24 CPV Capacitor electrolytic) connected in so there IS a greater loss In the IC.
Therefore, be careful not to exceed the
parallel
allowable loss.
Diode for the charge pump. An electric
11 CP1 . trr = 100 ns (max.) charge equal to the diode's er
High-speed . '
12 CP2 diode CRH01 (trr = 35 ns max.) component goes out of the capacitor's
24 CPV recommended charged electricity. Therefore, use a high-
speed diode.
22 OUT1 Gate resistor for external power MOSFET.
20 OUT2 Resistor - Choose the optimum value by considering
17 OUT3 the switching loss and EMI of the power
16 OUT4 MOSFET.
This is needed when the M + or M - pin
is biased to the negative side by more
than 0.5V from the SGND voltage.
10 SGND VF = 0.5V (max.) Because. ZthIS‘lCd operates relatciive toh SGND,
21 M + SBD CRSO3 (VF = 0.45V max. a parasitic Io e exists tewar .eac pm.
23 M - @0.7 A) recommended When the. M '. or M - pin IS biased to
the negative side by more than 0.5V from
SGND, the parasitic diode conducts,
causing the IC to operate erratically or
generate abnormal heat.
This is needed when the M + or M - pin
21 M + Resistor - is biased to the negative side by more
23 M - than 0.5V from the SGND voltage. This is
used to limit current for external SBD.
2000-03-02 15/17
TOSHIBA TPD7202F
TENTATIVE
USAGE PRECAUTIONS
(Note 1) : About taking the charge pump voltage to external devices
Current can be taken out of the charge pump's final stage (CPV pin) to external devices
without causing any problem. In this case, because the charge pump voltage drops,
increase the capacitance of the capacitor connected to the CPV pin. However, this may
cause the charging current to the capacitor and, hence, loss in the IC to increase. So be
careful not to exceed the allowable loss.
(Note 2) : About heat sink design
Because this IC contains a charge pump function, loss in it affects external capacitor
capacitance and diode characteristics. It is recommended that the junction temperature, Tj,
be judged from the on-voltage of the FAULT pin (open-drain). When VDD is within the
range of operating power supply voltages, the FAULT pin outputs a low. For details about
on-voltage characteristics, see Tj-l/FAULT characteristic curves.
(Note 3) : About dead time setting
For arm-shorting input logic, all outputs (OUT1-OUT4) are pulled low. When operating in
forward or reverse mode, consider the OUT1-OUT4 switching time and the switching time
(including temperature characteristic) of the external power MOSFET as you set the dead
time. The dead time required for only the IC, not including the external power MOSFET, is
4ps (within all operating power supply voltages and all operating temperatures).
(Note 4) : Shorting between outputs, Shortcircuit of outputs and VDD pin or Shortcircuit of outputs
GND pin may cause the IC to break down. Therefore, pay careful attention to the design
of output lines and VDD and GND lines.
(Note 5) : Precautions on dry packing
After unpacking dry or moistureproof packing, please make sure the device is mounted in
place within 48 hours at temperature and humidity of 30°C and 60% RH or less. Because
the device is emboss-taped and cannot be processed by baking, always be sure to use it
within said allowable time after unpacking.
Tape packing quantity: 500 devices/reel (EL) or 2000 devices/reel (EL1)
2000-03-02 16/17
TOSHIBA TPD7202F
TENTATIVE
PACKAGE DIMENSIONS
SSOP24-P-300-1.00B Unit : mm
fi4flFlFlfiilFlFlfiilflRFIFi "
6 OiO 2
8.0i0.3
£15? 'rssigyieei--------,
1.0TYP H 0.410.1_=m@
v, 13.5MAX t/
a 13.0:02 r/
cu. A e-.'c'cl.
ilk“ '?
1aosat,stccccsccci] 'it"' g ‘°
T''''" ,. 1",
_._.:L o
F- U'?,
Weight : 0.299 (typ.)
2000-03-02 17/17
:
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