TP3464N ,MICROWIRE Interface Device (MID)Block Diagram
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TP3464N
MICROWIRE Interface Device (MID)
APR I NG
giilli)l!),t,i,illii,f?gr,1g,il. "ELNle,l,tlleg,
Semiconductor
TP3464/TP3465 MlCROWiREi'" Interface Device (MID)
General Description Features
The MICROWlRErM Interface Device MID gives a general a Multiplexed and Non-multiplexed microprocessor bus
microprocessor (such as National Series 32000© proces- compatible
sors, Intel 800188, 80086 or 80286, Motorola 6800 and II National/Intel and Motorola microprocessor bus
68000 family of processors) the ability to communicate tttti- compatible
ciently with up to eight peripheral devices via the serial MI- I: Microprocessor Clock (CKIN) up to 20 MHz
CROWIRE interface. The MID causes each of the peripheral MICROWIRE clock speeds up to 5 MHz
devices to appear to the PP as memory mapped locations, Directly compatible with a- and 16-bit MICROWIRE
by performing all the data serialization and transfer proto- peripherals
cols to and from the peripherals. TP3464 for 4 Chip Select outputs (24-pin)
TP3465 for 8 Chip Select outputs (26-pin)
Memory mapped peripherals
Programmable MICROW|RE Clock to communicate with
devices of different speeds
Operates as MICROWIRE bus master or slave
24-pin Skinny-DIP pkg or 28-pin PLCC, DIP
n CMOS, Low Power
Applications
u ISDN Terminal Adapters
II Digital Line cards (ISDN and Non ISDN)
" Analog Linecards using National COMBO IITM
u Interfacing to industry standard serial EEPROMs
u Interfacing to industry standard MICROWIRE peripheral
devices such as Analog to Digital Converters, LCD driv-
ers, clock generators
Block Diagram
Microprocessor 65V MICROWIRE
Interface Interface
CKIN COUNTER ' SK
burst elk (8 or 16)
tiff/os
Frrt/(it/R)
Microprocessor Interface
Control
Reglsters
or AO-S (i/p)
TP3465 only
(28 pin pkg)
tw (24 pin pkg)
TL/H/10803-1
FIGURE 1. MICROWIRE Interface Device MID
Series 32000' and TRl-STATE' are registered trademarks at National Semiconductor Ctvtxrration.
COMBO “W and MICROWIREW are trademarks of National Semiconductor Corporation.
91990 National Semiconductor Corporation TLlH/10803 I RRD-B2OM110/Printed in U, S. A.
(GIIN) 9°!A9Cl aoeuetw EIHIMOHOIW 9978d1/79178d1.
Connection Diagrams
24-Pin Skinny DIP 28-Pin PLCC
100-1 U 24-1 "dtriaiid,y'i'i).",,
ADI- 2 23 --0S3
ADz- 3 22 -cs2 A04 --CSt
A03- 4 21 -csl CSUAO -cso
AIM- 5 20 “050 h05 mass -ey"
A05- 6 TP3464 19 -rert ADS MID - RST
Athi- 7 MID 18 -hs/ut CS5/ht ~As/u1
hor- 8 17 '-c-E AD? -csti/A2
i - __ - vTR/(R/W) --tTr
wR/(R/W)- 9 16 *HULT/INT
itTr/0s- 10 15 -CKIN -
SK-H 14-5. i(a,'s?'Fo'''''7't'sl;t,
tmoe 12 " -So ' l;
TL/H/10803 2 TL/H/10803-3
Top View Top View
Order Number TP3464N Order Number TP3465V
See NS Package Number N24C
See NS Package Number V28A
FIGURE 2. MICROWIRE interface Device MID
28-Pin DIP
A00- 1 28 -ecc
At)t- 2 27 -css
h02- s 26 -cs2
A03- 4 25 -cs1
Mu-- 5 24 -cs0
CS4 M-. s 23 -CS7 "
/t,',t" 7 TP3465 22 Cii7
A06- e 21 -AS/ul
Css/AI- 9 20 -CS6/A2
A07- to 19 -tTt
'Tit/tttN)- 11 18 -Tucrmt
KT/trs- 12 17 -c1
sx- 13 16 ~51
cun- 14 15 -so
TL/H/10803-14
Top View
Order Number TP3465N
See NS Package Number N288
' TP3464/65 Pinouts
Pin Description
Pin No. Pin No.
Name 24 Pkg. 28 Pkg. Type Function
Vcc 24 28 I + 5V Supply
GND 12 14 I 0V
CKIN 15 17 I Master Clock Input Used to Derive the SK Clock
MICROWIRE Interface
The MICROWIRE Interface consists of SK (clock out), SO (data out), SI (data in) and up to 8 chip select output lines.
Pin No. Pin No.
Name 24 Pkg. 28 Pkg. Type Function
SK 11 13 O MICROWIRE clock output.
so 13 15 0/l MICROWIRE data output. Can also be used for
MICROWIRE data input when communicating with special
devices. See application section.
SI 14 16 I MICROWIRE data input.
CSO-CS3 20-23 24-27 1/0 Four input/output lines, normally used as outputs for chip
selects to MICROWIRE peripherals
084-087 6, 9, 20, VD Four additional chip select lines accessible only in 28-pin
23 package and when using the Multiplexed bus mode.
Multiplexed Microprocessor Bus Interface
The MULT/W pin is sampled on power-up and, it LOW, the microprocessor bus format is assumed to be Multiplexed and the
pin is considered an input pin to indicate Multiplexed bus format. The pin has an internal pulI-up and thus it pin is left floating, it
will be considered as in Non-multiplexed mode. The interface consists of an eight bit multiplexed Address/Data microprocessor
bus (only the A0, A1, A2 and A3 address lines are decoded), and six control lines (W, TCT, AS/ MI, At5/ DS, vm (R /W) and the
MULT input) which should be tied LOW.
Pin No. Pin No.
ame 24 Pkg. 28 Pkg. Type Function
ADO-AD? 1-8 1, 2, 3, 4, HO Address/ Data bus. Transfers addresses and data
5, 7, 8, 10 between the microprocessor and the MID.
tRt- 17 19 I Chip Enable. A LOW on this signal selects the MID tor a
Read/Write operation.
WAV 9 11 I Write or Read-Write direction. This signal indicates a Write
R/W operation or Read/Write direction signal.
AD/DS 10 12 I Read or Data Strobe. This signal indicates a Read
operation or a Data strobe signal.
AS/MI 18 21 I Address Latch Enable or Address Strobe. A HIGH on this
line indicates an address on the external A/ D bus. When
MULT = 1 (non-multiplexed bus), the pin indicates the
type of bus, MI = 1 for NSC/intel format and MI = 0, for
Motorola format.
RST 19 22 I The RST is the master Reset input, when LOW forces the
device in the RESET condition (same as Power-on-
Reset).
MULT/ 16 18 I Multiplexed Bus input or INTerrupt output. It is internally
W pulled HIGH to indicate a Non-Muitiplexed bus format and
needs to be pulled LOW externally to indicate the
Multiplexed bus format.
Non-Multiplexed Microprocessor Interface
The MU-LT/IN-T pin is sampled on power-up and, if not LOW, the microprocessor bus format is assumed to be Non-multiA?xed.
ms intert_ace consists_(_)f a four-bit Address bus, an eight-bit Data bus and six control lines (CE RST, AS/MI, RD/DS,
WR/(R/WR) and the INT signal if enabled).
Pin No. .
Name 28 Pkg. Type Function
A0-A3 6, 9, l Address bus. These 4 pins (accessible in the 28-pin package)
20, 23 are used to address the 16 registers.
DO-D? l, 2, 3, 4, l/O Data bus for data transfer between the microprocessor and the
5, 7, 8, 10 MID.
E 19 Chip Enable. A LOW on this signal selects the MID for a
Ftead/Write operation.
VW/ 11 Write or Ftead-Write direction. This signal indicates a Write
(Ft/W) operation or Read/Write direction signal.
FTI5/DS 12 Read or Data Strobe. This signal indicates a Read operation or a
Data Strobe signal.
AS/MI 21 t Address Latch Enable or Address Strobe. A HIGH on this line
indicates an address on the external A/ D bus. When MULT=1
(non-multiplexed bug), the pin indicates the type of bus, MI = 1
for NSC/Intel format and MI = 0 for Motorola format.
Non-Multipiexed Microprocessor Interface (Continued)
The MULT/W pin is sampled on power-up and, if not LOW, the microprocessor bus format is assured to be Non-muefxed.
This interface consists of a four-bit Address bus, an eight-bit Data bus and six control lines (CE RST, AS/Ml, RD/DS,
W/(Ft/W) and the W signal if enabled).
Pin No. .
Name 28 Pkg. Type Function
RST 22 l The RST is the master Reset input; when LOW, it forces the
device in the RESET condition (same as Power-on-Reset).
MULT/ 18 l Multiplexed Bus input or INTerrupt output. It is internally pulled
Wt 0 HIGH to indicate a Non-multiplexed bus format and the pin can
be an IN-T output pin if enabled by setting the lnten bit in the
CKR register. Fir pulls low to indicate the completion of a
MICROWIRE transfer operation.
Functional Description
The block diagram of the MICROWIRE Interface Device
(MID) is shown in Figure 1. it essentially consists of a very
flexible microprocessor bus interface, a serial MICROWIRE
interface and a Chip Select (output) port. Internally it con-
tains a programmable clock divider to derive the MICRO-
WIRE clock speed from a system clock.
MICROPROCESSOR INTERFACE
The Microprocessor bus interface supports both National/
Intel and Motorola bus formats in the Multiplexed and Non-
multiplexed bus modes.
The MULT/W pin is sampled on power-up and, it LOW, the
microprocessor bus format is assumed to be Multiplexed
and the pin is considered an input pin to indicate Multi-
plexed bus format. The pin is internally pulled HIGH. Upon
sampling, if the pin is not LOW, the bus format is assumed
to be Non-multiplexed.
The microprocessor interface supports multiplexed Ad-
dress/Data Formats for the Intel 8088/80188 and Motorola
6803 families to work in 8-bit mode. Non-multiplexed busses
of the National 32000, Intel 80286 and Motorola 68000, se-
ries processors and similar are supported in the TP3465 28-
pin part. Four address lines allow access to all MID regis-
The MID incorporates a flexible bus interface logic to sup-
port the different address and data strobes required by the
different bus formats. The timing specifications are shown in
a later section. The following table shows microprocessor
bus control pin functions:
MICROWIRE COMMUNICATION MODES
The MID provides a MICROWIRE port to the main proces-
sor having two modes of operation with the MICROWIRE
peripherals. Software controlled chip select and hard-
ware generated chip select modes.
In the first scheme, besides the 2 data byte registers, there
is a third register which maps directly with the output CS
Chip Selects pins (4 in the TP3464 24-pin package and 8 in
the TP3465 28-pin package). The software in the microproc-
essor then writes to the CS register to select and deselect
individual bits (corresponding to pins).
In the second scheme, the CS pins are activated by a hard-
ware state machine when triggered by accessing the data
registers through other address locations (see section on
Register description). In this case the hardware will activate
the chip select pin, send the appropriate number of MICRO-
WIHE data bits (8 or 16) and then deselect the pin. This
enhanced mode of communication allows the MICROWIRE
peripheral devices to appear as it I/O mapped in the micro-
processor's memory space.
CONTROL AND DATA REGISTERS
There are 6 control registers (PD, MWM, SKP, SKR, ST and
CS), and 1 set of Data registers (First MICROWIRE Byte
FMB and Second MICROWIRE Byte SMB) for data com-
munication to MICROWIRE devices. In normal mode, the
Chip select pins CSO-C? are controlled (via the CS register)
by software and data is transferred via the FMB and SMB
registers located at address 01h and 00h (see Table l).
Eight additional addresses (FMBDO-7) access the same
data register (FMB) but provide additional information to
an internal state machine which drives appropriate chip se-
lect pins (e.g., FMBDO at address 02h controls CSO pin,
FMBD1 at address 03h controls CSI pin etc.). There is
only 1 set of Data registers (FMB and SMB) which han-
dle the MICROWIRE communication. This latter method
. NSC/Intel Bus Motorola Bus
MID Pin
MUXed Non-MUXed MUXed Non-MUXed
AS/MI ALE MI = 1 AS Ml = o
FTr5/rys FTO Wo DS DS
W/(R/W) WA W (H/W) (R/W)
of allocating special addresses to provide pin-select infor-
mation facilitates an enhanced MICROWIRE interface to
the host processor.
Table I summarizes the Control and Data Registers and the
addresses at which they are accessed.
Functional Description (Continued)
TABLE I. Control and Data Registers
Address Register Bit? Blt6 Bits Bit4 Bit3 Bit2 Bin BitO
00h SMB d7 d6 d5 d4 d3 d2 d1 d0
01h FMB d7 d6 d5 d4 d3 d2 d1 d0
02h FMBDO d7 d6 d5 d4 d3 d2 d1 d0
03h FMBD1 d7 d6 d5 d4 d3 d2 d1 d0
04h FMBD2 d7 d6 d5 d4 d3 d2 d1 d0
05h FMBD3 d7 d6 d5 d4 d3 d2 d1 d0
06h FMBD4 d7 d6 d5 d4 d3 d2 d1 d0
07h FMBDS d7 d6 d5 d4 d3 d2 d1 d0
08h FMBD6 d7 d6 d5 d4 d3 d2 d1 d0
09h FMBD7 d7 d6 d5 d4 d3 d2 d1 d0
0Ah CS cs7 cs6 cs5 cs4 cs3 cs2 cs1 csO
OBh SKP skp7 skp6 skp5 skp4 skp3 skp2 skp1 skp0
0Ch MWM mwm7 mwm6 mwm5 mwm4 mwma mwm2 mwm1 mme
ODh SKR inten soi ms 0 0 div2 div1 divO
OEh ST uwdone 0 0 0 O 0 0 0
OFh PD pd? pd6 pd5 pd4 pd3 pd2 pd1 pd0
PD-pin Definition Register: W Register MWM-MlCROWlRE Mode Register: W Register
RESET condition is FFhex (all pins as Inputs) RESET condition is 00hex
Bit7 Bits Bits em Bits Bit2 em Bito Bit? Bit6 Bits Bit4 Blt3 Blt2 Blt1 Bit0
pd7 pd6 pd5 pd4 pd3 pd2 pd1 pdo mwm7 mwm6 mwm5 mwm4 mwm3 mwm2 mwm1 mme
pd0-7 bits configure the CSO-7 pins as inputs or outputs.
For example pdo = 1, sets the CSO pin as an input; pdo =
0, sets CSO pin as an output. Upon chip RESET, the pd0-7
bits are set to 1.
SKP--MlCROWIRE Clock (SK) Polarity: W Register
RESET condition is 00hex (Normal MICROWlRE clock)
mwm0-7 bits specify whether 8 or 16 clocks are generated
for devices connected to CSO-? pins. For example mwm1
= I, 16 clocks will be generated for device controlled by
CSI, (16 data bits will be shifted out and 16 data bits will be
strobed in); mwm0 = o, 8 clocks will be generated for de-
vice controlled by CSO (8 data bits will be shifted out and
strobed in).
SKR--M1CR0WME Clock (SK) Rate Register:
skp 0-7 bits set the polarity of the SK MICROWIRE clock
when communicating with device connected to each of the
pins CSO-?. For example skp0 2 0, normal MICROWIRE
mode (Le, so data output on negative edge of SK clock)
when sending data to device controlled by CSO pin; skp1 =
I, NSC COMBO ll clock format for device controlled by CS1
(Le., so data output on the positive edge of SK clock).
W Register
Bit7 Bits Bits Bit4 Bits Bit2 Bit1 Bito
inten soi ms 0 0 div2 div1 divO
The 3 bits divO-2 give the divide-by value for deriving the
SK clock output rate from the CKIN. The maximum CKIN
rate is 20 MHz, and the slowest MICROWIRE peripheral
works at 256 kHz. Table 2 below gives the division ratios
and some examples:
div2 div1 divo SK Ratio e.g., CKIN : 5 MHz e.g., CKIN = 20 MHz
0 0 0 SK = CKIN SK = 5 MHz
0 0 1 SK = CKIN/2 SK = 2.5 MHz
0 1 0 SK = CKlN/4 = 1.25 MHz SK = 5 MHz
0 1 1 SK = CKIN/8 = 625 kHz = 2.5 MHz
1 O 0 SK = CKlN/16 = 312.5 kHz = 1.25 MHz
1 0 1 SK = CKIN/32 = 156.25 kHz = 625 kHz
1 1 0 SK = CKlN/64 = 78.125 kHz = 312.5 kHz
1 1 1 SK = CKlN/128 = 39.06 kHz = 156.25 kHz
TABLE 2. SK Clock Rate Control
Functional Description (Continued)
The uwdone bit in the ST register can be connected to the
lNTerrupt pin of the MID to alert the host processor when
MICROWIRE transmission is completed by setting the inten
bit in this SKR register. The Fit pin will only be functional as
an INTerrupt in the Non-multiplexed bus mode in the 28-pin
TP3465 device.
The soi bit configures the so pin to be output (sol = O) or
input (soi = 1). This bit function is used to perform a Read
operation on a device such as NSC TP3071 COMBI ll be-
cause the TP3071 sends data back on the so pin. When
soi = I, the so pin functions as the SI input pin, internally,
and feeds the data registers. See applications diagrams and
software procedures for more details.
The ms bit configures the MID device as a Master of MI-
CROWIRE (ms = O) or Slave of MICROWIRE (ms = 1).
MlCROWlRE Slave mode is described and illustrated in the
applications section.
CS-Chip Select Port Register: R/W Register
RESET condition, CS pins are inputs and the register con-
tains the state of these pins.
Blt7 Bit6 Bit5 Bit4 Blt3 Bit2 Bit1 BltO
cs7 cs6 cs5 cs4 cs3 cs2 cst csO
csO-7 bits control the 8, CS input/output port pins. Only
030-3 are available in TP3464 24-pin package and in the
TP3465 device when used in the non-multiplexed bus for-
mat. In the multiplexed bus format in TP3465, all 8 CS pins
are accessible.
Writing to this register will affect the pins (configured as
outputs in PD register) directly. Similarly, the state of the
pins which are configured as inputs in the PD registers can
be Read via the same (CS) register. When reading the pins
designated as outputs, the bits will have a "I" condition.
Writing to bits corresponding to input pins will have no effect
on the pins.
The state of an output chip select pin may also be con-
trolled by the chip hardware state machine if the user writes
to the FMBD0-7 registers. The hardware can only bring the
appropriate pin LOW for the duration of the MICROWIRE
transfer and will attempt to set it HIGH at the end of the
transfer. If the user has, however, set this pin to be LOW by
writing to this register, it will over-ride the action of the hard-
ware and the pin will remain LOW. Thus the user must write
a "I rt in the bits that will be controlled by hardware, and the
pins must be set as outputs in the PD register.
ST-MICROWlRE Status Register: R Register
RESET Condition, Read 80 Hex
Bit7 Bit6 Blt5 Blt4 Bit3 Blt2 Bit1 Bit0
uwdone 0 0 0 0 O 0 0
The uwdone bit (read only) in the ST register can be polled
by the software to determine the end of the MlCROWIRE
transmission (uwdone = 1). uwdone = 0 during transmis-
FMB-First MICROWIFIE Byte: R/W Register
Bit? Bit6 Blt5 Blt4 Bit3 Bit2 BIN Bit0
d7 d6 d5 d4 d3 d2 d1 d0
SMB-Second MICROWIRE Byte: R/W Register
Bit? Blt6 Bits Bit4 Bit3 Bit2 Blt1 BitO
d7 d6 d5 d4 d3 d2 d1 d0
The SMB and the FMB data registers are used to communi-
cate to any MICROWIRE device 0-7 (connected to pins
CS0-7) when controlling the chip select lines via CS regis-
ter (using software). The MICROWIRE parameters tor this
mode of operation are defined by the parameters for device
7, i.e., skp7 in SKP register, and mwm7 in MWM register.
So when communicating with peripherals requiring different
formats, the skp7 and mwm7 bits may need to be re-contig-
ured before sending data to each of these devices. Example
of communication to 8-bit and 16-bit peripherals are de-
scribed below:
Example 1: Communicating with an 8-bit MICROWIRE pe-
ripheral at CS1:
Set the skp7 bit to 0 (normal MlCFtOWlFtE polarity), and set
the mwm7 to 0 for 1 byte operation). Set cs1 bit to 0 to
select the device. Write the data into the FMB byte location
and it gets shifted out after the trailing edge of the Write
strobe signal. At the end of the MICROWIRE transmission.
Set the cs1 bit to 1 to de-select the device. The 8-bit
STATUS from the peripheral is Read from the FMByte loca-
Example 2: Communicating with a 16-bit MICROWIRE pe-
ripheral at CS3:
MICROWIRE protocol specifies that the Most Significant Bit
is transmitted first. Thus the HIGH byte of data becomes the
First MlCFtOWIRE Byte to be sent out.
Set the skp7 bit to 0 (normal MICROWIRE polarity), and set
the mwm7 to 1 for 2 byte operation). Set cs3 bit to 0 to
select the device. Write the LOW data byte in the SMB reg-
ister and then write the HIGH data byte into the FMB byte
location. All 16 data bits get shifted out after the trailing
edge of the Write strobe for the FMB register. At the end of
the MICROWIRE transmission. Set the csa bit to 1 to de-
select the device. The 16-bit STATUS from the peripheral is
Read from the FMB (HIGH data byte) and the SMB (LOW
data byte) locations.
FMBD0-First MICROWIRE Byte Devo: R/W Register
Bit7 Bit6 Bits Bit4 Bits Blt2 Bit1 Bito
d7 d6 d5 d4 d3 d2 d1 d0
There is only one set of data registers (FMB and SMB)
which handle the MICROWIRE data communication. The
FMBDO address accesses the data register FMB but also
provides information for the internal state machine to con-
trol the CSO pin. The MICROWIRE parameters for device 0
are indicated by the state of bits spr and mwm0, etc.
Functional Description (Continued)
Example I: Communicating with 8-bit peripheral-device 0:
The mwmo bit must be set to 0. Write the MICROWIRE
data in to the FMBDO address and the 8-bit data is shifted
out after the trailing edge of the write pulse. The Chip Select
(CSO) is automatically activated (LOW) and deactivated
(HIGH) by hardware before and after the data transfer (see
timing diagrams). The 8-bit STATUS from the peripheral is
read from the FMBDO byte location.
Example 2: Communicating with 16-bit peripheral-device
The mwmo bit must be set to 1. Write the LOW byte of
MICROWIRE data into the SMB data register and then write
the HIGH byte in to the FMBDO address. The 16-bit data is
then shifted out after the trailing edge of the write strobe
signal for this FMBDO address. The Chip Select 0 (CSO) pin
is automatically activated (LOW) and deactivated (HIGH) by
hardware before and after the data transfer (see timing dia-
grams). The 16-bit STATUS from the peripheral is Head
from the FMBDO (HIGH data byte) and the SMB (LOW data
byte) locations.
FMBD1-First MiCROWIRE Byte Dev1: R/W Register
Same function as FMBDO except this refers to Device 1 and
Chip Select 1 (CS1).
FMBD2-First MICROWIRE Byte Dev2: RI W Register
Same function as FMBDO except this refers to Device 2 and
Chip Select 2 (CS2).
FMBD3--First MICROWIRE Byte Deva: R/ W Register
Same function as FMBDO except this refers to Device 3 and
Chip Select 3 (CS3).
FMBD4-First MICROWIRE Byte Dev4: R/W Register
Same function as FMBDO except this refers to Device 4 and
Chip Select 4 (CS4),
FMBD5-First MICROWIRE Byte Dev5: R/W Register
Same function as FMBDO except this refers to Device 5 and
Chip Select 5 (CS5).
FMBD6-First MICROWIRE Byte Dev6: R/W Register
Same function as FMBDO except this refers to Device 6 and
Chip Select 6 (CS6).
FMBD7--First MICROWIRE Byte Dev7: R/W Register
Same function as FMBDO except this refers to Device 7 and
Chip Select 7 (CS7).
MICROWIRE Master/Slave Modes
MICROWIRE MASTER MODE
The primary application for MID is as a master of MICRO-
WIRE bus (ms bit in CKR register set to O), and as such it
provides the SK clock out to the peripheral devices. it trans-
mits data on the so pin and receives data on the SI pin. The
CSO-? pins are used as chip select pins for the peripherals
and have predefined relationship with the SK clock output.
Writing to the FMB pin causes the most significant bit to be
output immediately to the so pin and the uwdone bit is
reset to 0 by hardware. Upon completion of transfer of ei-
ther 8 bits (mwm7 = 0) or 16 bits (mwm7 = 1), the
uwdone bit is set to 1 by hardware. The SO pin is then
set to TRI-STATE© condition. Note that when using the
FMB and SMB registers, the communication mode is deter-
mined by the parameters for channel 7 (mwm7 and skp7),
MICROWIRE SLAVE MODE
The MID can be set to work in MICROWIRE Slave mode by
setting the ms bit to 1. The MICROWIRE clock from the
master is connected to the CKIN pin of this MID device. The
SK output is ignored. Normally the SO pin is in TRI-STATE
condition and while the uwdone bit is 1, any CKIN clock
inputs are ignored. Writing to the FMB register causes the
most significant bit to be output immediately to the so pin
and the uwdone bit is reset to 0 by hardware. The SK clock
input is then enabled to clock data into SI and out of so
pins. After receiving SK clock pulses; either 8 (mwm7 = 0)
or 16 bits (mwm7 = 1); the uwdone bit is set to 1 by hard-
ware. The SO pin is then set to TRI-STATE condition. Note
that when using the FMB and SMB registers, the communi-
cation mode is determined by the parameters of channel 7
(mwm7 and skp7).
FMBDO-7 addresses are not used in the slave mode. The
CS register, however, can be used as a general I/O port
control register.
See applications section for an example of the Slave opera-
tion (Figure 6).
MICROWIRE BUS FORMATS
MID supports devices which implement the two MICRO..
WIRE bus formats; a 3-pin format and a 4-pin format. Figure
3 shows a MID connected to devices supporting each of
these formats.
The standard 4-pin tormatt consists of the CCLK clock pin,
co and Cl as the data out and data in pins, and cs to select
the MICROWIRE peripheral. ISDN transceivers and other
intelligent peripherals also have an INTerrupt signal from
the peripheral to the local microprocessor. NSC MICRO-
WIRE devices with this 4-pin format include ISDN transceiv-
ers, COMBO ll, LCD display drivers and EEPROMs.
There are, however, some MICROWIRE peripherals (e.g.,
TP3071 COMBO II, and some EEPROMs) which support a
3-pin bus format because of package pin limitations. The
format consists of the CCLK clock signal, a bi-directional
data signal CO/CI, and a CS chip select signal. The direc-
tion of the data transferred on the CO/CI pin is determined
by a protocol between the Master and the Slave of the MI-
CROWIRE bus. For example, the TP3071 implements a
two-byte protocol. The first byte into the TP3071 indicates a
Head or a Write operation and thus defines the direction of
the next byte to the device.
Software Driver Procedures
This section describes the steps for software driver routines
to communicate with different MICROWIRE devices (8-bit,
16-bit, or more) and those supporting the 3-pin or 4-pin
MICROWIRE bus formats.
INiTIALlZATION
I. Write to PD (Pin Definition) register to set the desired chip
select control pins (CSO-7) as outputs. (All cs pins are
set to inputs on chip RESET.)
2. Write to SKP (SK polarity), to select the polarity of the SK
clock for each of the MICROWIFiE devices connected to
CSO-? pins.
3. Write to MWM (MICROWIRE Mode) register to select
whether 8- or 16-bit devices are attached to the CSO-?
pins. Devices needing more than 16-bits may still be con-
figured as 8-bit mode (if multiple of 8) or 16-bit mode (if
multiple of 16 bits).
Software Driver Procedures (Continued)
4. Write to SKR to set the div bits to support the fastest SK
clock rate supported by the peripherals. Set the inten bit
if the uwdone status is to set an INTerrupt to the host
processor (available only in the Non-multiplexed bus im-
plementation of TP3465, 28-pin package). The ms and
the sol bit are set to 0 upon power up and indicate that
the MID is in MICROWIFlE Master mode, with SO as an
output pin as normal.
SENDING DATA TO PERIPHERALS (Normal Mode)
Assume sending 16-bit data to a MICROWIRE based device
connected to any one of CSO to CS7.
1. Write to CS (Chip Select) register and RESET the appro-
priate bit and thus activate the corresponding CS pin.
2. Write LOW byte data to SMB (Second MICROWIRE Byte)
register and then HIGH byte data to FMB (First MICRO-
WIRE Byte) register.
3. Read the ST (Status) register and stay in a loop until
uwdone bit is set.
4. Write to CS register and Set the bit to deactivate the ap-
propriate chip select pin.
SENDING DATA TO PERIPHERALS
(Hardware Assisted Chip Select)
Assuming sending 16-bit data to dev3 connected to CS3
1. Write LOW byte data to address SMB and then HIGH
byte data to FMBDS.
2. Read the ST register and stay in a loop until uwdone bit
is set.
Communicating with an NSC
TP3071 COMBO II Type Device
The NSC TP3071 COMBO ll device has a modified MICRO-
WIRE port. It shares a single pin (called CO/Cl) for incoming
and outgoing data. The MID's so pin may be tied to this pin,
as shown in Figure J, and the following steps are followed
to Read from and Write to this device. Assume that the chip
select for TP3071 is connected to CSI pin.
TP3071 Write Operation:
a. Initialization states: skp1 = l, mwm1 = l, and soi = 0
b. Data transfer options:
i. Set cs1 bit to 0, write LOW byte to SMB, and HIGH
byte to FMB and then set cs1 bit to 1 after uwdone bit
is set to 1. OH
ii. Write LOW byte to SMB, and HIGH byte to FMBD1.
TP3071 Read Operation:
a. Initialization states: skp1 = l, mwm1 = O, and soi = 0.
b. Data transfer options:
i, Set ttsl bit to 0, write HIGH byte to FMB, wait until
uwdone bit is set to 1 by hardware. Set soi bit to 1.
Write dummy LOW byte (e.g., 00h) to FMB, wait until
uwdone bit is set to 1 by hardware. Read STATUS
from FMB address. Set soi to 0 and cs1 to l.
ii. Write HIGH byte to FMBD1, wait until uwdone bit is set
to 1 by hardware. Set soi bit to 1. Write a dummy LOW
byte (e.g., 00h) to FMBD1 and wait until uwdone bit is
set to 1 by hardware. Read STATUS from FMBD1 ad-
dress. Set soi bit to 0.
Applications
The TP3464/TP3465 MICROWlRE Interface Device can be
used in a number of applications involving MlCROWIRE pe-
ripheral devices that need to be controlled using a standard
microprocessor which only has a parallel bus structure.
ISDN TERMINAL ADAPTER
The MID can be used in ISDN terminal adapters (see Figure
4) interfacing to ISDN components such as TP3420 SID, as
well as non-ISDN components such as LCD display drivers
(e.g., COP470) and serial EEPROMs (COP494). In this ap-
plication the MID signals SK, SO and SI are bussed to all
peripheral devices. Chip selects lines (4 in the 24-pin pack-
age and 8 in the 28-pin package) are individually connected
to each of the devices. Status Interrupt from the peripherals
such as SlD are connected directly to the main processor.
ANALOG OR DIGITAL LINECARDS
The MID can also be used in analog and digital (ISDN and
Non-ISDN) linecard applications (see Figure 5). Up to 8
MICROWIRE peripheral devices (TP3070 COMBO II, or
TP3420 SIDS, TP3410 Ule or TP3401 DASLs) can be con-
nected to one MID device. The Interrupts from the trans-
ceivers may be wire-ORed and fed into one interrupt line of
the main processor, in which case all the devices will need
to be polled after an interrupt. The efficient interface be-
tween the MID and microprocessor allows this process to
be accomplished with minimum overhead.
In a given application, if any of the chip select pins are not
used to perform chip select for peripherals, then it may be
used as a general purpose input/output pin under software
control.
MID SUPPORTING MASTER AND SLAVE
MICROWIRE OPERATION
The MICROWIRE serial data bus is often used as a means
of inter-processor communication. The MID may be used
either as the Master of the MICROWIRE clock SK or as a
Slave to the SK clock fed via CKIN pin. Figure 6 shows an
application in which two general microprocessors communi-
cate with each other over the MICROWIRE bus. At the
same time other peripherals are also connected to the serial
bus. External handshaking between the two processors is
required before the MICROWIRE Byte data transfer is exe-
cuted by the master of the MICROWIRE bus.
Applications (Continued)
COMBO ll
TP3071
pP bus
IntoI/Motorola
TP3 420
Micro-
processor
24-pin Skinny DIP
FIGURE 3. MID, Two Types of Microwire Formats;
3-Pln (e.g., TP3071 COMBO II) and 4-Pin (e.g., TP3420, SID)
CSI MICROWIRE
SK, so, SI, cso-s
sto or
UID or
COMBO II
"S" or
2 B . 0 Serial Data stream
Serial
EEPROM
TP3451
driver
psp bus
Intel/Motorola
Micro-
processor
CSO-3 24 pin Skinny DIP
FIGURE 4. MID, TERMINAL EQUIPMENT Application
tThe nomenclature for MICROWIRE signal names is as follows:
MICROWIRE controller-SK (clock), so (data out), SI (data in)
MICROWIRE peripheral-CCI (clock). CO (data out), Cl (data in).
TL/H/10803-15
"U" Interface
TL/H/10803v4
Applications (Continued)
To Backplane Bus
Micro-
processor
Sysiom
Control
CS7 w, so, SI. cso-7
SID or
UID or =
DASL or . .
COMBO ll 1 2 B i) Serial Data stream
SID or 4
UID or ,
DASL or
COMBO ll 4
SID or N
UID or '
DASL or t Wi -
COMBO II A lntorrup s Ire ORed
-iiir,r14 MICROWIRE -
SID or SK INT =
UID or ' 1 SI C_E
DASL or t 1
couao ll 4 so MID
CS3 A_k
Sli) or N CSF? 28 pin PLCC, DIP pf' bus
UID or ' lnteI/Motorola
DASL or
couao ll 1
SK so SI
CS2 ' '
" CSO-7
SID or N
Oli) or ,
DASL or
COMBO ll "
SID or <
UID or ,
DASL or
COMBO ll ",
SID or G
Oli) or '
DASL or
COMBO ll "
FIGURE 5. MID, LINECARD Application-Digital (lSDN/Non-ISDN) or Analog
TL/H/10803-5
Applications (Continued)
MASTER
tThe nomenclature for MICROWIRE signal names is as follows:
MICROWIRE controller-SK (clock), so (data out), SI (data in)
MICROWIRE porting-CCI (clock), CO (data out), CI (data in).
CO EEPROM
Cl DISPLAY
CCLK DRIVER
FIGURE 6. Example of MID in Master or Slave MICROWIRE Operation
TL/H/10803-6
Device Electrical Characteristics
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
t9tfitte/Dlatributttrs for availability and specificatlons.
Vcc to GND 7V
InputVoltage -0.3Vto Vcc + 0.3V
DC Input Current I. i 50 mA
Storage Temperature Range -65"C to + 150°C
Lead Temperature
(Soldering, 10 Sec.) 300°C
ESD Rating, to be determined
Electrical Characteristics
Unless otherwise noted, limits in BOLD characters are electrical testing limits at Vcc = 0.5V and TA = + 25°C. All other limits
are design goals for Vcc =, 5.0V :5% and TA = 0°C to + 70°C. All signals are referenced to GND. This data sheet is still
preliminary and parameter limits are not indicative of characterization data with respect to power supply or temperature varia-
tions. Please contact your National Semiconductor Sales Office for the most current product information.
Symbol Parameter Conditions Limits Units
Min Max
" Input Low Voltage All Inputs 0.8
V.H Input High Voltage All Inputs 2.0
VOL Output Low Voltage CSO-T. IOL = 1 mA
SK, SO: IOL = 4 mA 0.4 V
AD(7:O): lot. = 2 mA
VOH Output High Voltage CSO-P. lor, = 1 mA
SK, SO: IOH = 4 mA 2.4 v
AD(7:0): IOH = 2 mA
IIH High Level Input Current All Inputs,
- 1 o A
GND < VIN < Vcc P
IIL Low Level Input Current All Inputs + " p.A
'02 Output Current in High-Z AD(7:0), SO i 20 MA
ICC Dynamic Supply Current CKIN = SK = 1 MHz 0.7 mA
CKIN = SK = 20 MHz 4
Timing Characteristics
This section contains timing diagrams for the microprocessor bus interface, MICROWIRE port interface and the Control and
Clock timings relationships.
Timing characteristics are guaranteed from worst-case simulations plus guardbanding. Production testing is limited to device
functionality.
NSC/lntel Bus Format
MULTIPLEXED MICROPROCESSOR BUS
AS (ALE) t
---, t WASHj
tsus ----
Address
OR of FF) and tTt
(Road cycle)
OR of V752 and c‘:
(Write cycle)
NON-MULTIPLEXED MICROPROCESSOR BUS
As/ut = 1 (NSC, INTEL bus format)
gt"-'"'-.,-
Data F--
trase I km, tmm
t R-....-".;-' t
HASW HWO
u---tum
'WWL ---
TL/H/10803-7
A0-3 ----1" Address I
00-7 ----f"-""iotTti'i-"Tsg-
tue tmm trm,
- - ---i, t 1
((213 Cg,'? CE tur, L WR: I ie: -
OR of Fit and tTi s"'-,'.'':--.-,,); -
(Write cycle)
TL/H/1080378
Symbol Parameter Conditions Min Max Units
tWASH Width, Address Strobe High 20 ns
iSAAs Setup, Address to Address Strobe 10 ns
tHASA Hold, Address Strobe Low to Address 10 ns
thASR Hold, Address Strobe to Read Strobe 10 ns
tDRD Delay, Wad Low to Data 100 pF Load 70 ns
tHRD Hold, A-eil' High to Data 5 40 ns
tWRL Width, Tea? Strobe Low 20 ns
tsow Setup, Data to W_ritE High 30 ns
tHWD Hold, 77"rit7, High to Data 10 ns
tWWL Width, WIT; Strobe Low 20 ns
ISAR Setup, Address to ATird Low Non-Muxed, Ml = 10 ns
tHRA Hold, Ai% High to Address Non-Muxed, Ml = 10 ns
tSAW Setup, Address 10% Low Non-Muxed, MI = 1 10 ns
tHWA Hold, W-rite- High to Address Non-Muxed, Ml = 1 10 ns
Motorola Bus Format
MULTIPLEXED MICROPROCESSOR BUS
0R ofD_S and (TE
ADO-7 Add ress
NON-MULTIPLEXED MICROPROCESSOR BUS
AS/Ml = 0 (Motorola bus format)
Ao-s ----4
tsAtrs
Address
onoHTSandcT ls,
TL/H/10803<9
tsewtrs - tHOSA
R/w si (Rad)
(WM Uses
TL/H/10808-10
Symbol Parameter Conditions Min Max Units
tWASH Width, Address Strobe High 20 ns
ISAAS Setup, Address to Address Strobe 10 ns
tHASA Hold, Address Strobe Low to Address 10 ns
tHASDS Hold, Address Strobe to Data Strobe 10 ns
tDDSD Delay, m Low to Data (Read) 100 pF Load 70 ns
tHDSD Hold, Bat-astro-tre High to Data 5 40 ns
tWDSL Width, Da-tagiro-toe Low 20 ns
tSDDS Setup, Data to m High (Write) 30 ns
lsnwos Setup, R/W Strobe to Data Strobe 10 ns
tHDSRw Hold, Data Strobe to H/ W 10 ns
tSADS Setup, Address to Data-trobe Low Non-Muxed, MI = 0 10 ns
tHDSA Hold, t5Tiia-giFim High to Address Non-Muxed, Ml = O 10 ns
MICROWIRE Timing Diagrams
Symbol Parameter Conditions Min Max Units
fCKIN CKin Frequency 20 MHz
fSK SK Frequency 5 MHz
tSKD SK Clock Duration 200 ns
tSKH SK High Duration 70 ns
tSKL SK Low Duration 70 ns
tRSK Rise Time, SK 100 pF Load 30 ns
tFSK Fall Time, SK 100 pF Load 30 ns
tSISK Setup Time, SI Valid to SK Edge 20 ns
tHSKI Hold Time, SK High to SI Invalid 20 ns
105m Delay, SK Edge to so Data Valid Output 20 ns
tDSKZ Delay, Last SK to so TRI-STATE 30 ns
tDwov Delay, WR to SO Valid FMB or 50 ns
FMBDO-7
MICROWIRE Timing for 1 Byte Transfer
Tit (rua.ruaoo-7)
_-\J tacswa
—"'\ tosxcsh
CSO- 7 -
(auto mode)
-.. - tsxo tsm " I
SK (skp0-7--0) or
s-tttsoo-r--" _ I
Sl M7X°X5 ( X X 'i''', l
H trtsm
si-tOCP/ri-il-cr), _-
- krsrr
- - "a,
HID (First Microwiro 8m)
TU/H/lov-ll
MICROWIRE Timing for 2 Byte Transfers
7it (rua,ruaDo-7)
C$0-7 /
sj/r)(s)s)(4)(a)(a)(i)(a)(n(s)( X XIXzX‘Xt’W
X X7X°X5X‘X=X X XX)-
so-( 7 X 6 X 5 I . X3 2 l, I O
TL/Fi/Iii-li?
nm (flat Mlcrowln Byte) 5MB (Second Ilcrovtlro Byn)
Control Interface Timing Relationships
Symbol Parameter Conditions Min Max Units
tDWCSA Delay, Write Strobe to CS Asserted Auto Mode 2 SK Cycle
tDCSSKA Delay, CS Active to first SK Edge Auto Mode 0.5 SK 0.5 SK ns
- 50 ns
tDSKCSA Delay, Last SK Edge to CS Inactivate Auto Mode 0.5 SK 0.5 SK ns
- 50 ns
tchss Delay, Write Strobe (CS Register) Software 30 ns
to CS Asserted
tDCSN Delay, CS High to W Low 50 ns
tDRDN Delay, W Low to W High ST Register 80 ns
OR of W and CT -1cyf
W l i .
( n o) or oquv - Mm tixam -
Chip Select -_
!INIT \
OR of ii) and c? N-C"
R d . . t
( ea ) or equw ttmoe OSK2
so output - /////// /
Last SK pulse
TL/H/t0803- 1 3
Physical Dimensions inches(millimeters)
. 1,N3-1170
0092 (31.57-32.Nl
12.3311 1w
it Pttl " " [tt m
1. tli31 Mt OPTION t T
Pitt " t ~/ (th piu) 025010.005
WW (A. M0 (550410.121)
J' = - I
/mmmw 5 mm a mummnm
otmtm 2 IMtit 5.1501011 nus
th300 _ th3211 [1575) OPTIONAL
(h62-8.It8) RAD 0.040
“-0151 0130:0005
"P" '1 (3.302+0.1z71m
_1__" I l - L11L-.0_.tt.E 0.200
rlt,iilys'-3'---leg-) 13.683- 5.0001
thim-ILM l T—i‘
(0I29-0.381) ..tril_65 l
(1.851) - tIAN-trt"
0. 01510. 00:1 73.115 4.5551
+tl.MO 0015:0015 L " _ie-rz-itiy-l---
0.325 mm
-0015 (100510.301) (045110 0101 12+ o
(0.2551'33) 0100:0010 90 t4 "P
- . l (2.54:0.2541
NZAC (REV F)
Molded Dual-ln-Llne Package (N)
Order Number TP3464N
NS Package Number N24C
FlirrlriillRlRfRFlfTfRfRlRrrlfRlR
1 /tTsTs) .
0.51020.“
(1235:1127)
[jTltlLC1lLslltlLrJltlL0trll0.rjyAl.el
PIN N0. 1 IDENT
‘ iM.38-3thtm
0. 000 "m-thtml tl.ulr-tr.N 0._ 050
10 1521 J-_-ttAX (1S.N- 15.151 (u83-5.M4) (l. 2101 .-rTrt' 1ln_eir_iLtfli,
(3.1Tli- 0.191) 0020
5 -ir- 1 l 1 (a 5001""
f 1 ______L
95.19 A tMOS-tMIS . .
tr=s8td - (thtt9-0.3811 86 M m
MM----- 005010.015 0 100:0. 010 th 010:0 000
(M. 7rs, (m‘. l-- 12.50010 J.-edl-f,1--i I--- -l V-te-hte',','-,',- 051100151 y,-2,'sflli'-3'-i.
0. 025 t: :12: I . - . I
fs "til m) an! (REV Et
Molded Dual-ln-Line Package (N)
Order Number TP3465N
NS Package Number N283
TP3464/TP3465 MICROWIRE Interface Device (MID)
Physical Dimensions inches (millimeters) (Continued)
li SPACES "
(1.270)
Lit. # 113997
" (5.2301
nun scum:
VIEW l-A
(1.14:1) nus
x 45" (1.1“)
-0ir-91l.r, oo- n. m
irtui-rtrri)
(comm nmzusmu)
.°_- tlt0 I-s,,)?'''''''':"'''-')
Il____. tm- tl. MO (u 503) (9331:4451) 11.165411”
Io. "'1'iL1iijs'i'i,r-', um m (4.191 4.5121
ooos M15 L—L%}=ififififinsfln i)Tl''CC..rC..
$.10 12?- o. 3811 il 1
muu.1_‘;_> I MtN-thit3t iCs__ucl 0.115
mm (thti60-0, M3) 'i2=saz-irsm
“"50 Te
' [11.43)
- Ai-Let. van mm B)
(12.32-12.57)
Plastic Chip Carrier (V)
Order Number TP3465V
NS Package Number V28A
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NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR
USE AS CRITICAL COMPONENTS Pl LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
to the user.
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Datasheets for electronic components.
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This file is the datasheet for the following electronic components:
TP3464N - product/tp3464n?HQS=T|-nu|l-nulI-dscatalog-df-pf—nuII-wwe
TP3465N - product/tp3465n?HQS=T|-nu|l-nuII-dscatalog-df—pf—nuII-wwe
