TP3056J ,7 V, parallel interface CODEC/filter COMBOFunctional Description
CLOCK AND DATA BUS CONTROL
The CLK input signal provides timing for th ..
TP3056J ,7 V, parallel interface CODEC/filter COMBOGeneral Description
The TP3051, TP3056 family consists of a p-law and A-Iaw
monolithic PCM CODE ..
TP3056J ,7 V, parallel interface CODEC/filter COMBOBlock Diagram
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TQ2-3V , 2-pole 5 mm Surface Mount Relay, JIS C0806 compliant Measurement equipment
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TQ2-4.5V , 2-pole 5 mm Surface Mount Relay, JIS C0806 compliant Measurement equipment
TQ2-6V , 2-pole 5 mm Surface Mount Relay, JIS C0806 compliant Measurement equipment
TQ2-9V , 2-pole 5 mm Surface Mount Relay, JIS C0806 compliant Measurement equipment
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TP3051J-TP3056J
7 V, parallel interface CODEC/filter COMBO
National
_ Semiconductor
TP3051, TP3056 Parallel Interface
CODEC/Filter COMBO@
General Description
The TP3051, TP3056 family consists of a y-iaw and A-law
monolithic PCM CODEC/filter set utilizing the A/D and D/A
conversion architecture shown in Figure 1 and a parallel VO
data bus interface. The devices are fabricated using Nation-
al’s advanced double poly microCMOS process.
The transmit section consists of an input gain adjust amplifi-
er, an active RC pre-filter, and a switched-capacitor band-
pass filter that rejects signals below 200 Hz and above
3400 Hz. A compressing coder samples the filtered signal
and encodes it in the IL-255 law or A-iaw PGM format. Auto-
zero circuitry is included on-chip. The receive section con-
sists of an expanding decoder which reconstructs the ana-
log signal from the compressed w-law or A-law code, and a
low pass filter which corrects for the sin x/x response of the
decoder output and rejects signals above 3400 Hz. The re-
ceive output is a single-ended power amplifier capable of
driving low impedance loads. The TP3051 p-law and
TP3056 A-Iaw devices are pin compatible parallel interface
COMBOs for bus-orianted systems.
F eatu res
I: Complete CODEC and filtering system including:
- Transmit high pass and low pass filtering
- Receive low pass Mer with sin x/x correction
- Receive power amplifier
- Active RC noise filters
-- p255 law COder and DECoder--TP3051
- A-law COder and DECoder--TP3056
- Internal precision voltage reference
- Internal auto-zero circuitry
" Meets or exceeds all LSSGR and CCITT specifications
I: , 5V operation
I! Low operating power-tYP/y 60 mW
n Power-down standby moda-typically 3 mW
a High speed TRI-STATE© data bus
I: 2 Ioopback test modes
Block Diagram
AuTD-IEID
ANALOG A A F.
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m anon anon E cu Fcimm. TL/H/8834-1
FIGURE 1
9908c”. ‘lSOSdJ.
TP3051,TP3056
Connection Diagrams
Dual-ln-Llne Package
tin - 1 l , 20 llhl'
tmM--, 2 19 - ml-
wht) - 3 18 - GS:
ma-- 4 17 - Vccu
M- 5 mm " - irisi/ctat
Mr- a "3055 15 - tut
086- 7 " -- 080
085 - a 13 - MI
mu ...- 9 It - Mt
li00-1 10 11 033
TLfH/8834-3
Top View
Order Number TP3051J or TP3056J
See NS Package Number J20A
Pin Description
Symbol
Function
Negative power supply pin. VBB = -5V k 5%.
Analog ground. All analog signals are refer-
enced to this pin.
Analog output of the receive power amplifier.
This output can drive a 600n load to i 2.5V.
Positive power supply voltage pin for the ana-
log circuitry. VOCA = 5V 15%. Must be con-
nected to Vcctr
Device chip select input which controls READ,
WRITE and TRl-STATE® operations on the
data bus. cs does not control the state of any
analog functions.
Bit 7 I/O on the data bus. The PCM LSB,
Bit 6 I/O on the data bus.
Bit 5 l/O on the data bus.
Bit 4 l/O on the data bus.
Digital ground. All digital signals are referenced
to this pin.
Bit 3 l/O on the data bus.
Bit 2 I/O on the data bus.
Bit 1 1/0 on the data bus.
Bit 0 l/O on the data bus. This is the PCM sign
The clock input for the switched-capacitor til.
ters and CODEC. Clock frequency must be
768 kHz, 772 kHz, 1.024 MHz or 1.28 MHz and
must be synchronous with the system clock in-
Symbol Function
PCM/CNTL This control input determines whether the in-
formation on the data bus is PCM data or con-
trol data.
VCCD Positive power supply pin for the bus drivers,
VCCD Cut 5V i5%. Must be connected to
GSX Analog output of the transmit input amplifier.
Used to externally set gain.
VFxl- Inverting input of the transmit input amplifier.
VFXI + Non-inverting input of the transmit input amplifi-
Functional Description
CLOCK AND DATA BUS CONTROL
The CLK input signal provides timing for the encode and
decode logic and the switched-capacitor filters. It must be
one of the frequencies listed in Table I and must be correct-
ly selected by control bits co and CI.
CLK also functions as a HEAD/WRITE control signal, with
the device reading the data bus on a positive half-clock cy-
cle and writing the bus on a negative half-clock cycle, as
shown in Figures 4a and 4b.
POWER-UP
When power is first applied, power-on reset circuitry initializ-
es the COMBO and sets it in the power-down mode. All
non-essential circuits are deactivated and the data bus out-
puts, DB0--DB7, and receive power amplifier output, VFRO,
are in high impedance states.
The TP3051, TP3056 is powered-up via a command to the
control register (see Control Register Functions). This sets
Functional Description (Continued)
the device in the standby mode with all circuitry activated,
but encoding and decoding do not begin until PCM READ
and PCM WRITE chip selects occur.
TABLE I. Control Blt Functions
Control Bits Function
CO. C1 Select Clock Frequency
CO Ct Frequency
0 X 1.024 MHz
1 0 0.768 MHz or 0.772 MHz
1 1 1.28 MHz
C2, C3 Digital and Analog Loopback
C2 c3 Mode
1 X digital Ioopback
0 1 analog Ioopback
0 0 normal
C4 Power-Down/ Power-Up (Note I)
1 = power-down
0 = power-up
C5 TP3051-Don't care (Note I)
TP3056
1 = Not implemented. Do not use.
0 = A-law with even bit inversion
C6-C7 Don't Care (Note 1)
Note 1: These bits are always set to logical "I" when reading back the
control register.
DATA BUS NOMENCLATURE
The normal order for serial PCM transmission is sign bit first,
whereas the normal order for serial data is LSB first. The
parallel data bus is defined as follows:
Data Type DB0 DB7
PCM Sign Bit LSB
Control Data CO C7
READING THE BUS
ll CLK is low when trs goes low, bus data is gated in during
the next positive half-clock cycle of CLK and latched on the
negative-going transition. ll W/CNTL is low during the
falling CtT transition, then the bus data is defined as PCM
voice data, which is latched into the receive register. This
also functions as an internal receive frame synchronization
pulse to start a decode cycle and must occur once per re-
ceive frame, i.e., at an 8 kHz rate.
If pttM/CNTL is high during the falling c-s transition, the bus
data is latched into the control register. This does not affect
frame synchronization.
WRITING THE BUS
If CLK is high when tTi goes low, at the next falling tran-
sition of CLK, the bus drivers are enabled and either the
PCM transmit data or the contents of the control register are
gated onto the bus, depending on the level of PCM/CNTL
at the tTg transition. If PCM/CNTL is low during the c-s tall-
ing transition, the transmit register data is written to the bus.
An internal transmit frame synchronization pulse is also
generated to start an encode cycle, and this must occur
once per transmit frame; i.e., at an 8 kHz rate.
If PCM/CNTL is high during the cs falling transition, the
control register data is written to the bus. This does not
affect frame synchronization.
The receive register contents may also be written back to
the bus, as described in the Digital Loopback section.
Except during a WRITE cycle, the bus drivers are in TRI-
STATE mode.
CONTROL REGISTER FUNCTIONS
Writing to the control register allows the user to set the
various operating states of the TP8051 and TP3056. The
control register can also be read back via the data bus to
verify the current operating mode of the device.
1. CLK Select
Since one of three distinct clock frequencies may be
used, the actual frequency must be known by the device
for proper operation of the switched-capacitor fitters. This
is achieved by writing control register bits co and C1,
normally in the same WRITE cycle that powers-up the
device, and before any PCM data transfers take place.
2. Digital Loopback
in order to establish that a valid path has been selected
through a network, it is sometimes desirable to be able to
send data through the network to its destination, then
loop it back through the network return path to the origi-
nating source where the data can be verified. This loop-
back function can be performed in the TP3051 or TP3056
by setting control register bit C2 to 1. With C2 set, the
PCM data in the receive register will be written back onto
the data bus during the next PCM WRITE cycle. In the
digital Ioopback mode, the receive section is set to an idle
channel condition in order to maintain a low impedance
termination at VFRO.
3. Analog Loopback
In the analog Ioopback mode, the transmit filter input is
switched from the gain adjust amplifier to the receive
power amplifier output, forming a unity-gain loop from the
receive register back to the transmit register. This mode
is entered by setting control register bits C2 to 0 and C3
to 1. The receive power amplifier continues to drive the
load in this mode.
4. Power-Down/Power-Up
The TP3051 or TP3056 may be put in the power-down
mode by setting control register bit C4 to 1. Conversely,
setting bit C4 to 0 powers-up the device.
TRANSMIT FILTER AND ENCODE SECTION
The transmit section input is an operational amplifier with
provision for gain adjustment using two external resistors,
see Figure 2. The low noise and wide bandwidth allow gains
in excess of 20 dB across the audio passband to be real.
ized. The op amp drives a unity-gain fitter consisting of a
2nd order RC active pre-filter, followed by an 8th order
switched-capacitor bandpass filter clocked at 256 kHz. The
output of this filter directly drives the encoder sample-and-
hold circuit. The AID is of companding type according to
pt-255 law (TP3051) or A-Iaw (T P3056) coding schemes. A
precision voltage reference is trimmed in manufacturing
9908dl 'lSOSdl
TP3051, TP3056
Functional Description (Continued)
to provide an input overload (WAX) of nominally 2.5V peak
(see table of Transmission Characteristics). Any offset volt-
age due to the filters or comparator is cancelled by sign bit
integration in the auto-zero circuit.
The total encoding delay referenced to a PCM WRITE chip
select will be approximately 165 its (due to the transmit
filter) plus 125 #5 (due to encoding delay), which totals 290
DECODER AND RECEIVE FILTER SECTION
The receive section consists of an expanding DAC which
drives a 5th order switched-capaoitor low pass filter clocked
TO TRANSMIT
FIIJER
TL/H/8834-4
R1 + R2)
Set gain to provide peak overload level = tMAX at GSx (see Transmission
Characteristics)
FIGURE 2. Transmit Gain Adjustment
Non-inverting transmit gain = 20 10910 (
at 256 kHz. The decoder is of A-law (T P3056) or p-law
(T P3051) coding law and the 5th order low pass filter cor-
rects for the sin x/x attenuation due to the 8 kHz sample/
hold. The filter is then followed by a 2nd order RC active
post-fiiter. The power amplifier output stage is capable of
driving a 6000 load to a level of 7.2 dBm. See Figure a The
receive section has unity-gain. Following a POM READ chip
select, the decoding cycle begins, and 10 p5 later the de-
coder DAC output is updated. The total decoder delay is _
10 p8 (decoder update) plus 110 p.s (filter delay) plus 62.5
#5 (% frame), which gives approximately 180 ps.
mo 300 N"
Maximum output power = 7.2 dBm total, 4.2 dam to the load.
a M iiBm
VFID R1
TLIH18834-5
See Applications information for attenuator design guide.
FIGURE 3. Receive Galn Adjustment
Absolute Maximum Ratings
If MiiltaryfAerospaee specified devices are required,
please contact the National Semiconductor Sales
Offlce/Dlstrlbutors for availability and specifications.
GNDD to GNDA
VCCA or VCCD to GNDD or GNDA
V35 to GNDD or GNDA
Voltage at Any Analog
Input or Output
Electrical Characteristics
Unless otherwise noted: VOCA = Vccp = 5.0V i5%, V33 = --5V i5%, GNDD = GNDA = 0V, TA = trc to 70'C; typical
characteristics specified at nominal supply voltages, TA = 25°C; all digital signals are referenced to GNDD, all analog signals
are referenced to GNDA. Limits printed in BOLD characters are guaranteed tor VCCA = VCCD = 5.0V 1 5% and V35 = -6.0V
1 5%; TA = 0°C to 70°C by correlation with 100% Electrical testing at TA = 25'C. All other limits are assured by correlation with
other production test and/or product design and characteristics.
Voltage at Any Digital
Input or Output
Operating Temperature Range
vcc+ 0.3V to GNDD--0.3V
--25% to + 125°C
k 0.3V Storage Temperature Range - 65°C to + 150'C
7V Lead Temp. (Soldering, 10 sec.) 30ty'C
- 7V ESD (Human Body Modal) 1000V
Vcc + 0.3V to V35 -0.3V
Symbol j Parameter Conditions T Mln I Typ I Max I Units
DIGITAL INTERFACE
" input Low Voltage 0.8 V
VIH Input High Voltage 2.2 V
VOL Output Low Voltage DB0-DB7, IL = 2.5 mA 0.4 V
VOH Output High Voltage DBO-DB7, IH "u1.T -2.5 mA 2.4 V
IIL Input Low Current GNDD S VIN S " -3 a FLA
IIH Input High Current VIH S VIN S Vcc --a a MA
'02 Output Current in High Impedance DBO-DB7, GNDD S Vo S Vcc _ tt 3 " A
State (TRI-STATE)
ANALOG INTERFACE WITH TRANSMIT INPUT AMPLIFIER
IIXA Input Leakage Current -2.5V S V S +2.5V. VFxl+ or VFxl- --200 200 nA
RIXA Input Resistance --2.5V S V S +2.5V, VFXI+ or VFxl- 10 Mn
ROXA Output Resistance, GSX Closed Loop, Unity Gain 1 3 ft
RLXA Load Resistance, GSx 10 kn
CLXA Load Capacitance, GSX 50 pF
VoXA Output Dynamic Range, GSx RL = 10 kn -a.tt 2.8 V
AVXA Voltage Gain VFXI + to 68x 5000 V/ V
FUXA Unity-Gain Bandwidth 1 2 MHz
VosXA Offset Voltage - 20 20 mV
VCMXA Common-Mode Voltage CMRRXA > 60 dB - 2.5 2.5 V
CMRRXA Common-Mode Rejection Ratio D.C. Test tttt dB
PSRRXA Power Supply Rejection Ratio D.C. Test 60 dB
RECEIVE POWER AMPLIFIER
HORF Output Resistance, VFRO 1 3 n
RLRF Load Resistance VFRO = i2.5V 600 n
CLRF Load Capacitance 50 pF
VOSRO Output DC Offset Voltage - 200 200 mV
POWER DISSIPATION
lcco Power-Down Current No Load (Note I) 0.5 1 .s mA
I330 Power-Down Current No Load (Note 1) 0.05 0.3 mA
'CC1 Active Current No Load 6.0 9.0 mA
lest" Active Current No Load 6.0 9.0 mA
Note r. loco and Iago are measured after frrst achieving a power-up state.
9908d1 'LSOSdJ.
TP3051, TP3056
Timing Specifications
Unless otherwise noted: VCCA = Vch = 5.0V i5%, V53 = -5V 15%, GNDD == GNDA = 0V, TA = O'C to 70‘C; typical
Characteristics specified at nominal supply voltages, TA = 25''C; all digital signals are referenced to GNDD, all analog signals
are referenced to GNDA. Limits printed in BOLD characters are guaranteed for VCCA = VCCD = 5.0V 1 5% and Vim = -5.0V
k5%; TA = tPC to 70°C by correlation with 100% Electrical testing at TA = 25°C. All other limits are assured by correlation with
other production test and/or product design and characteristics. All timing parameters are measured at VOH = 2.0V and VOL =
0.7V. Sea Definitions and Timing Conventions section for test method information.
Symbol Parameter Condltlons Mln Max Units
tpc Period of Clock 760 ns
tWCH Width of Clock High 330 ns
tWCL Width of Clock Low 330 ns
trec Rise Time of Clock 50 ns
th Fall Time of Clock 50 ns
tHccs Hold Time trom CLK to CE Low 1 tttt ns
tSCLc Sat-Up Time of t% Low to CLK 1 00 ns
tSCHC Set-Up Time from a High to o ns
Second CLK Edge
twcs Width of Chip Select 100 ns
KSPCM Set-Up Time of PCM/CNTL to ES 0 ns
tHPCM Hold Time from TS to PCM/CNTL 1 00 ns
tspc Set-Up Time of Data In to CLK BO ns
IHCD Hold Time from CLK to Data In 20 ns
tDDo Delay Time to Data Out Valid CL == 0 pF to 200 pF " 260 ns
tDDz Delay Time to Data Output Disabled G. = 0 pF to 200 pF 20 80 ns
Switching Time Waveforms
het, hec
m I f F-"
- qas tsac --h,
ttrcs I tsax
(Mom) 'i-------'
ism - ttea,
FTS/ CNTL
I---- tooo ---- cm; -e -
Deo-oa7 qllllllllliliilts mm our
TIJH/8834-6
FIGURE 4a. Tlmlng Waveforms tor COMBO Writing to the Bus
cut 8 Z d:
8CCS ‘ws tsax
Es "'-""'-""-'''s .
(norm) 4..----.-.--.'
tseas 1-h = iimctt -..
m/cm watt '1lllllillllL
tsa: u.
080-087 '1lllillll mm mm
TL/ H/8B34-7
restriction.
FIGURE 4b. Tlmlng Waveforms for COMBO Reading from the Bus
Note 2: READ and WRITE 3 pulses must each occur at an 8 kHz rate, and may occur on consecutive halfcycles of CLK it required, although this is not a
Transmission Characteristics
Unless otherwise specified: TA = WC to +70°C, VCCA = VCCD = SV 15%. V35 = --5V i5%, GNDD = GNDA = 0V,f =
1.02 kHz, VIN = 0 dBmO, transmit input amplifier connected for unity-gain non-inverting. Limits printed in BOLD characters are
guaranteed for VCCA = VCCD == 5.0V 15% and V33 = --5,0V t5%; TA = 0°C to 70°C by correlation with 100% electrical
testing at TA = 25°C. All other limits are assured by correlation with other production tests and/ or product design and character-
istics.
Symbol Parameter l Conditions L Min I Typ I Max I Unlts
AMPLITUDE RESPONSE
Absolute Levels Nominal 0 dBmO Level is 4 dBm
(6000)
0 dBmO TP3051 1.2276 Vrms
TP3056 1.2276 Vrms
tMAx Maximum Overload Level TP3051 (+ 3.17 dBmO) 2.501 VpK
TP3056 ( + 3.14 dBmO) 2.492 VpK
GXA Transmit Gain, Absolute TA = 25"C,VccA = V000 = 5.0V,
V33 = -5.0V -o." OAS dB
Input at GSX = 0 dBmO at 1020 Hz
Gxn Transmit Gain, Relative to GXA f = 16 Hz -40 dB
f = 50 Hz -30 dB
f = 60 Hz -26 dB
f= 200 Hz --N.tt -OA dB
f = 300 Hz-3000 Hz - 0.15 0.15 dB
1: 3300 Hz -u.as 0.1 dB
f = 3400 Hz -O.T 0 dB
f = 4000 Hz - " dB
t = 4600 Hz and Up, Measure Response - " dB
from 0 Hz to 4000 Hz
GXAT Absolute Transmit Gain Variation Relative to GXA
' -0.1 0.1 dB
with Temperature
GXAV Apsolute Transmit Gain Variation Relative to GXA _ 0.05 o.os dB
with Supply Voltage
Grow Transmit Gain Variation with Sinusoidal Method
Level Reference Level = -- 10 dBmO
VFxl+ = --40 dBmo to +3 dBmO --o.2 0.2 dB
VFXI+ = -50 dBmO to --40 dBmO -O.4 0.4 dB
VFxl+ '= -55 dBmO to -50 dBmO - 1.2 1.2 dB
GRA Receive Gain, Absolute TA = 25''C, VCCA = VCCD = 5V, V53 = -5V
Input = Digital Code Sequence for - 0.1 s 0.1 5 dB
0 dBmO Signal at 1020 Hz
GRR Receive Gain, Relative to GRA f = 0 Hz to 3000 Hz - 0.1 s 0.1 s dB
f = 3300 Hz --0.as 0.05 dB
f = 3400 Hz -O.T o dB
= 4000 Hz - 14 dB
Gan Absolute Receive Gain Variation Relative to GRA
. - 0.1 0.1 dB
with Temperature
GRAV Apsolute Receive Gain Variation Relative to GHA _ 0.05 o.os dB
with Supply Voltage
GRRL Receive Gain Variation with Sinusoidal Test Method; Reference
Level Input PCM Code Corresponds to an
Ideally Encoded - 10 dBmO Signal
PCM Level ' -40 dBmO to +3 dBmO -o.2 0.2 dB
PCM Level = -50 dBmO to -40 dBmO -O.4 0.4 dB
PCM Level = -55 dBmO to -50 dBmO - 1.2 1.2 dB
Vno Receive Output Drive Level RL = 6000 -2.5 2.5 V
9908:”. ‘l-QOSdJ.
TP3051, TP3056
Transmission Characteristics (Continued)
Unless otherwise specified: TA == 0°C to 4-70''C, VCCA = VCCD = 5V t5%, VBB = -5V K5%, GNDD = GNDA = ov, f =
1.02 kHz, VIN = 0 dBmO, transmit input amplifier connected for unity-gain non-inveriing. Limits printed in BOLD characters are
guaranteed for VOCA = VCCD = 5.0V k5% and veg = -5.OV f5%; TA = 0°C to 70°C by correlation with 100% electrical
testing at TA = 25''C. All other limits are assured by correlation with other production tests and/ or product design and character-
istics.
Symbol Parameter Conditions T Min I Typ I Max I Units
ENVELOPE DELAY DISTORTION WITH FREQUENCY
DXA Transmit Delay, Absolute f = 1600 Hz 290 315 yt'
DXR Transmit Delay, Relative to DXA f = 500 Hz-600 Hz 195 220 ps
f = 600 Hz-800 Hz 120 145 ps
f = 800 Hz-1000 Hz 50 75 ps
f = 1000 Hz-1600 Hz 20 40 p.s
f = 1600 Hz-2600 Hz 55 75 ps
f = 2600 Hz-2800 Hz 80 105 Hs
f = 2800 Hz-aooo Hz 130 155 #5
DRA Receive Delay, Absolute f = 1600 Hz 180 200 ps
DRR Receive Delay, Relative to ORA f = 500 Hz-tooo Hz -40 -25 ps
f = 1000 Hz-1600 Hz -30 -20 us
t = 1600 Hz-2600 Hz 70 90 p.s
f TTT 2600 Hz-2800 Hz 100 125 113
f = 2800 Hz-3000 Hz 145 175 ps
Nxc Transmit Noise, C Message TP3051, (Note 3)
Weighted 12 " dBrnCO
pr Transmit Noise, P Message TP3056, VFXI+ = 0V (Note 3) - _
Weighted 74 69 dBmOp
Nag Receive Noise, C Message TP3051, PCM Code Equals Alternating 8 1 , dBrnCO
Weighted Positive and Negative Zero
Nap Receive Noise, P Message TP3056, PCM Code Equals Positive _ _
Weighted Zero 82 " damop
an Noise, Single Frequency f = 0 kHz to 100 kHz, Loop Around _ 53 dBmO
Measurement, VFXI + = 0V
PPSRX Positive PowerSupply VFXI+ = 0V,
Rtsieetion,Transmit VCCA = VCCD = 5.0 VDC + 100 mes 40 dBC
f = 0 kHz-50 kHz (Note 4)
NPSRX Negative Power Supply VFXI+ = 0 Vrms,
Reiection. Transmit V33 = -5.0 VDC + 100 mVrms 40 dBC
f = 0 kHz-50 kHz (Note 4)
PPSRR Positive Power Supply PCM Code Equals Positive Zero for
Rejection, Receive TP3051 and TP3056
Vcc = 5.0 VDC + 100 mVrms
f = 0 Hz-4000 Hz " dBC
f = 4 kHz-25 kHz 40 dBc
f = 25 kHz-50 kHz " dBc
NPSRR Negative Power Supply PCM Code Equals Positive Zero for
Rejection, Receive TP3051 and TP3056
V33 = -5.0 VDC + 100 mVrms
f = 0 Hz-4000 Hz 40 dBC
f = 4 kHz-25 kHz 40 dBc
f = 25 kHz-tio kHz " dBc
SOS Spurious Out-of-Band Signals O dBmO, 300 Hz-3400 Hz Input Applied to
at the Channel Output 1/Fxl +, Measure Individual Image Signals at
4600 Hz-7600 Hz - " dB
7600 Hz-8400 Hz -40 dB
8400 Hz-100,000 Hz - 32 dB
Transmission Characteristics (Continued)
Unless otherwise specified: TA = 0°C to +70''C, VCCA = VCCD = 5V A5%, V88 = -5V 15%, GNDD == GNDA = 0V, f =
1.02 kHz, VIN = 0 dBmO, transmit input amplifier connected for unity-gain non-inverting. Limits printed in BOLD characters are
guaranteed for VOCA = VCCD = 5.0V i5% and V33 = -5.OV i5%; TA = 0°C to 70°C by correlation with 100% electrical
testing at TA = 25''C. All other limits are assured by correlation with other production tests and/ or product design and character-
istics.
Symbol Parameter Conditions l Min I Typ I Max I Units
DISTORTION
STDx Signal to Total Distortion Sinusoidal Test Method (Note 5)
STDR Transmit or Receive Level = 3.0 dBmO " dB
Half-Channel = 0 dBmO to - 30 dBmO " dB
= --40 dBmO XMT " dB
RCV ao dB
= -55 dBmo XMT " dB
RCV 1 s dB
SFDX Single [frequency Distortion, - " dB
Transmit
SFDR 1me Frequency Distortion, - " dB
Receive
IMD Intermodulation Distortion VFxl + = -4 dBmO to -21 dBmO,
Two Frequencies in the Range - 4 1 dB
300 Hz-3400 Hz
CROSSTALK
CTX-m Transmit to Receive Crosstalk f = 300 Hz-3400 Hz at 0 dBmO Transmit _ 90 - TO dB
0 dBmO Transmit Level Level Steady PCM Receive Code
CTR_X Receive to Transmit Crosstalk f = 300 Hz-3400 Hz at 0 dBmO _ 90 - " dB
0 dBmO Receive Level (Note 2)
Note 3: Measured try extrapolation from the distortion test result at -50 dB m0.
Note 4.. CTR-» PPSRX. and NPSRX are measured with a - 50 dBm0 activation signal applied at VFxI +.
Note s.. Devices are measured using 0 message weighted filter for p-Iaw and psophomlic weighted filter for A-Iaw.
Encoding Format at Data Bus Output
TP3056
":22: True A-Law, cs = 0
" (Includes Even Blt Inversion)
MSB LSB MSB LSB
VIN = + Full-Scale 1 0 0 0 0 0 tl O 1 t) 1 O 1 0 1 0
VtN--=+0V1111111111010101
N%---OV 0111111101010101
VtN---Full-Scale O 0 0 0 0 0 0 0 o 0 1 0 1 0 1 0
9908:”. ‘l-SOSdJ.
TP3051, TP3056
Applications Information
POWER SUPPLIES
While the pins of the TP3051/6 family are well protected
against electrical misuse, it is recommended that the stan-
dard CMOS practice be followed, ensuring that ground is
connected to the device before any other connections are
made. In applications where the printed circuit board may be
plugged into a "hot" socket with power and clocks already
present, an extra long ground pin in the connector should
be used. GNDA and GNDD MUST be connected together
adjacent to each COMBO not on the Connector or back-
plane wiring.
All ground connections to each device should meet at a
common point as close as possible to the GNDA pin. This
minimizes the interaction of ground return currents flowing
through a common bus impedance. 0.1 pLF supply decou-
pling capacitors should be connected from this common
ground point to VCCA and V33.
For best performance, the ground point of each COMBO on
a card should be connected to a common card ground in
star formation, rather than via a ground bus. This common
ground point should be decoupled to VCC and V39 with
10 pF capacitors.
T-Pad Attenuator
sou .r"Gi'"'""-5ir- M
————-d|—
__....
_.__ - -_l
) TL/ H/ 8834 "
RI---?
" Nil-l
R2 2122(N2_1)
Wher :N _ POWER IN
tF.' y POWER OUT
Also: 2 = /z-sci-roc
Where ZSC = Impedance with short circuit termination
and 200 x Impedance with open circuit termination
w-Pad Attenuator
TL/ H/8834-9
v Z NI?
N2 - 1
R4= zt(N-s-l1'iis1-,-,)
FIGURE 5. T-Pad and anad Attenuator Models
The positive power supply to the bus drivers, Vccts is pro-
vided on a separate pin from the positive supply for the
CODEC and filter circuits to minimize noise injection when
driving the bus. VCCA and VCCD MUST be connected to-
gether close to the CODEC/filter at the point where the
0.1 pF decoupling capacitor is connected.
RECEIVE GAIN ADJUSTMENT
For applications where a TP3050 family COMBO receive
output must drive a 6000 load, but a peak swing lower than
i2.5V is required, the receive gain can be easily adjusted
by inserting a matched T-pad or n-pad at the output. (See
Figure 5.) Table II lists the required resistor values for 6000
terminations. As these are generally non-standard values,
the equations can be used to compute the attenuation of
the closer practical set of resistors. It may be necessary to
use unequal values for the R1 or R4 arms of the attenuators
to achieve a precise attenuation. Generally it is tolerable to
allow a small deviation of the input impedance from nominal
while still maintaining a good return loss. For example a
30 dB return loss against 600n is obtained if the output
impedance of the attenuator is in the range 282n to 3190
(assuming a perfect transformer).
TABLE II. Attenuator Tahies for 21 = 22 = Mon
(All Values in ft)
dB R1 R2 R3 R4
0.1 1 .7 26k 3.5 52k
0.2 3.5 13k 6.9 26k
0.3 5.2 8.7k 10.4 17.4k
0.4 6.9 6.5K 13.8 13k
0.5 8.5 5.2K 17.3 10.5k
0.6 10.4 4.4K 21.3 8.7k
0.7 12.1 3.7k 24.2 7.5k
0.8 13.8 3.3K 27.7 6.5k
0.9 15.5 2.9K 31.1 5.8k
1.0 17.3 2.6k 34.6 5.2K
2 34.4 1.3k 70 2.6K
3 51.3 850 107 1.8K
4 68 650 144 1.3k
5 84 494 183 1.1 k
6 100 402 224 900
7 1 15 380 269 785
8 379 284 317 698
g 143 244 370 630
10 156 21 1 427 527
1 1 168 184 490 535
12 180 161 550 500
13 190 142 635 473
14 200 125 720 450
15 210 1 10 816 430
16 218 98 924 413
18 233 77 1.17k 386
20 246 61 1.5k 366
Note: See Application Note 370 for further details.
This datasheet has been :
www.ic-phoenix.com
Datasheets for electronic components.
National Semiconductor was acquired by Texas Instruments.
corp/docs/irwestor_relations/Pr_09_23_201 1_national_semiconductor.html
This file is the datasheet for the following electronic components:
TP3051J - product/tp3051j?HQS=TI-null-nu|I-dscatalog-df-pf-null-wwe
TP3056J - product/tp3056j?HQS=T|-null-nu|I-dscatalog-df-pf-nuII-wwe
