TP3023J ,7V, monolithic CODECElectrical Characteristics Unless otherwise anéa TA = 0''C to 70°9ch = 5.0V t 5%, Visss = - 5.0V t ..
TP3040AJ ,TP3040/ TP3040A PCM Monolithic FilterFeaturesYDesigned for D3/D4 and CCITT
TP3040AN ,TP3040/ TP3040A PCM Monolithic FilterFeaturesYDesigned for D3/D4 and CCITT
TP3040J ,TP3040/ TP3040A PCM Monolithic FilterTP3040,TP3040APCMMonolithicFilterSeptember1994TP3040,TP3040APCMMonolithicFilterGeneralDescription
TP3040V ,TP3040/ TP3040A PCM Monolithic FilterTP3040,TP3040APCMMonolithicFilterSeptember1994TP3040,TP3040APCMMonolithicFilterGeneralDescription
TP3051J ,7 V, parallel interface CODEC/filter COMBOPin Description
Symbol Function
V33 Negative power supply pin. VBB = -5V : 5%.
GNDA Analog ..
TPSV107K025R0100 , Low ESR series of robust Mn02 solid electrolyte capacitors
TPSV477M010R0060 , 60-A, 3.3/5-V INPUT, NONISOLATED WIDE-OUTPUT ADJUST POWER MODULE
TPSW226K016R0500 , TPS Series Low ESR
TPSX107K010R0150 , Low ESR series of robust Mn02 solid electrolyte capacitors
TPU3040 , Teletext Processors
TQ2-3V , 2-pole 5 mm Surface Mount Relay, JIS C0806 compliant Measurement equipment
TP3023J
7V, monolithic CODEC
National
Semiconductor
July 1983
TP3022ITP3023 Monolithic CODECS
General Description
The TP3022 and TP3023 are monol'u l ' M CODECs im-
plemented with double-poly achnology. The
TP3022 is intended for A-Iaw applications. The TP3023 is
intended for u-Iaw applications.
Each device contains separate D/A and A/D circuitry, all
necessary sample and hold capacitors, a precision volt-
age reference and internal auto-zero circuit. A serial con-
trol port allows an external controller to individually
assign the PCM input and output ports to one of up to 32
time slots or to place the CODEC into a power-down
mode. Alternately, the TP3022/TP3023 may be operated
in a fixed time slot mode. Both devices are intended to be
used with the TP304O monolithic PCM filter which pro-
vides the input anti-aliasing function for the encoder and
smoothes the output of the decoder and corrects for the
sin x/x distortion introduced by the decoder sample and
hold output.
Features
ll Low operation power-45 mW typical
" Low standby power-I mW typical
l: t 5V operation
ll TTL compatible digital interface
II Time slot assignment or alternate fixed time slot modes
I: Internal precision reference
" internal sample and hold capacitors
ll Internal auto-zero circuit
ll TP3022-A-law coding, pin compatible with TP3020
II TP3023-w-law coding, pin compatible with TP3021
" Synchronous or asynchronous operation
LC: x) ttyi)
Simplified Block Diagram
SAMPLE AND HOLD
3625‘ WY'"
AUTO-ZERU
COMPAHAYOR
SAMPLE AND HOLD
TRI-STATE' is a registered trademark of National Semsconduclor Corp.
CONTROL
TL/H/szzsrv
531983 National Semiconductor Corp, TLIH15228
I 1WB20M73/Prmier1 in USA
s(DEICIOS ONIHOUOW SZOSdl/ZZOSdJ.
Absolute Maximum Ratings
Operating Temperature
StorageTemperature
Vcc with Respect to GNDD
Vcc with Respect to V33
V33 with Respect to GNDD
Voltage at Any Analog Input
or Output
Voltage at Any Digital Input
or Output
Lead Temperature(Soldering, 10 seconds)
- 25°Cto + 125°C
- 65°C to +150°C
Vat, - 0.3V to Vcc + 0.3V
GNDD - 0.3V to Vcc + 0.3V
DC Electrical Characteristics Unless otherwise n6? TA = 0°C to 70‘193Vcc = 5.0V t 5%, V33 = - 5.0V A 5%.
Typical characteristics are specified at Vcc = 5.0V, V33 = - 5.0V an
analog signals are referenced to GNDA.
Tr---erermf aigital signals are referenced to GN DD. All
Symbol Parameter Conditions Min Typ Max Units
DIGITAL INTERFACE
I, Input Current 0
" Input Low Voltage 0.6 V
VIH Input High Voltage 2.2 V
VOL Output Low Voltage Dx, loc = 4.0 mA 0.4 V
EGR‘ IOL=O.5 mA 0.4 V
TSX, IOL = 3.2 mA, Open Drain 0.4 V
PDN, tou--- 1.6 mA 0.4 V
VOH Output High Voltage Dx, IOH = 6 mA 2.4 V
SIGR, IOH=0.6 mA 2.4 V
ANALOG INTERFACE
a I/Fx Input Impedance when Resistance in Series with 2.0 "
Sampling Approximately 70 pF
Zo Output Impedance at VFR -3.1VVos Output Offset Voltage at VFR DR = PCM Zero Code (TP3023) - 25 25 mV
or Alternating tl Code (TP3022)
IIN Analog Input Bias Current VIN = 0V - 0.1 0.1 tdi
R1 x C1 DC Blocking Time Constant 4.0 ms
C1 DC Blocking Capacitor 0.1 "
R1 Input Bias Resistor 160 k0
POWER DISSIPATION
‘cco Standby Current, Vcc 0.1 0.4 mA
I530 Standby Current, VBB 0.03 0.1 mA
Iccl Operating Current, Vcc 4.5 8.0 mA
Iss, Operating Current, N/ms 4.5 8.0 mA
AC Electrical Characteristics Unless otherwise noted, the analog input is a 0 dBmO, 1.02 kHz sine wave. The
digital input is a POM bit stream generated by passing a 0 dBm0,1.02 kHz sine wave through an ideal encoder. All output levels
are sin x/x corrected.
Symbol Parameter Conditions Min Typ Max Units
Absolute Level The nominal 0 dBmO levels for
the TP3022 and TP3023 are
1.525 Vrms and 1.520 Vrms re-
spectively for the decoder and
1.560 Vrms and 1.555 Vrms
respectively for the encoder.
This corresponds to a loop gain
of -th2 as. All gain measure-
ments for the encode and de-
code portions of the TP3022/
TP3023 are based on these
nominal levels after the
necessary sin x/x corrections
are made.
GRA Receive Gain, Absolute T=25°C, Vcc=5V, -0.175 0.175 dB
V38 = - 5V
GRAT Absolute Receive Gain T = 0''C to 70°C - 0.05 0.05 dB
Variation with Temperature
GRAV Absolute Receive Gain Vcc = 5V t 5% - 0.07 0.07 dB
GXA Transmit Gain, Absolute T=25''C, Vcc=5V, V38: --5V -0.175 0.175 dB
GXAT Absolute Transmit Gain T=0''C to 70°C -0.05 0.05 dB
Variation with Temperature
GXAV Absolute Transmit Gain Vcc = 5V A 5%, - 0.07 0.07 OB
Variation with Supply Voltage VBB = - 5V t 5%
GRAL Absolute Receive Gain CCITT Method 2 Relative
Variation with Level to - 10 dBmO
00Bm0 t03dBm0 -0.3 0.3 dB
-40 dBmO to OdBmO -0.2 0.2 dB
-50 dBmO to -40 dBmO -0.4 0.4 dB
-55 dBmO to -50 dBmO -1.0 1.0 dB
GXAL Absolute Transmit Gain CCITT Method 2 Relative
Variation with Level to -10 JBm0
0 dBmO to 3 dBmO - 0.3 0.3 dB
-40dBm0to0 dBmO -0.2 0.2 dB
-50 0Brn0 to -40 dBmO -0.4 0.4 JB
-55 dBmO to -50dBm0 -1.0 1.0 dB
S/DR Receive Signal to Distortion Sinusoidal Test Method Input
Ratio Level
- 30 dBmO to 0 dBmO 35 dBc
- 40 dBmO 29 dBc
- 45 dBmO 25 dBc
S/Dx Transmit Signal to Distortion Sinusoidal Test Method Input
Ratio Level
- 30 dBmO to 0 dBmO 35 dBc
- 40 dBmO 29 dBc
- 45 dBmO 25 dBc
NR Receive Idle Channel Noise DR = Steady State PCM Code 6 dBrncO
Nx Transmit Idle Channel Noise TP3023, l/Fx = ov 13 dBrncO
TP3022, VFx = 0V - 66' dBmOp
HDR Receive Harmonic Distortion 2nd or 3rd Harmonic - 47 dB
HDx Transmit Harmonic Distortion 2nd or 3rd Harmonic - 47 dB
AC Electrical Characteristics (Continued) Unless otherwise noted, the analog input is a 0 dBm0, 1.02 kHz sine
wave. The digital input is a PCM bit stream generated by passing a 0 dBm0,1.02 kHz sine wave through an ideal encoder. All
output levels are sin x/x corrected.
Symbol Parameter Conditions Min Typ Max Units
PPSRX Positive Power Supply Input Level = 0V, Vcc = 5.0 hoc: 50 dB
Rejection, Transmit + 200 mVrms, f=1.02 kHz
PPSRR Positive Power Supply Dn =Steady PCM Code, 40 dB
Rejection, Receive Vcc = 5.0 VDc + 200 mVrms,
1:1.02 kHz
NPSRx Negative Power Supply Input Level = 0V, l/iss = -5.0 Voc 50 dB
Rejection, Transmit +200 mVrms, f=1.02 kHz
NPSRR Negative Power Supply DR: Steady PCM Code, 45 dB
Rejection, Receive V83 = -5.0 Voc + 200 mVrms,
f: 1.02 kHz
CTXH Transmit to Receive Crosstalk DR = Steady PCM Code - 75 dB
CTRX Receive to Transmit Crosstalk Transmit Input Level = 0V
TP3023 - 70 dB
TP3022 - 65' dB
"Theoretical worst-case for a perfectly zeroed encoder with alternating sign bit, due to the decoding law.
Timing Specifications Unless otherwise noted, TA=0''C to 70''C, Vcc--- 5.0: 5%, - -5.0 15%. All digital
signals are referenced to GNDD and measured at " and VIH levels as indicated in the Timing Waveforms.
Symbol Parameter Conditions Min Typ Max Units
tpc Period of Clock CLKc, CLKR, CLKX 485 ns
tRc, th Rise and Fall Time of Clock CLKC, CLKR, CLKx 30 ns
tWCH Width of Clock High CLKC, CLKR, CLKx 165 ns
tWCL Width of Clock Low CLKC, CLKR, CLKx 165 ns
tan, AID Conversion Time From End of Encoder Time 16 Time
Slot to Completion of Slots
Conversion
tom DIA Conversion Time From End of Decoder Time 2 Time
Slot to Transition of VFR Slots
tsoc Set-Up Time, Dc to CLKC 100 ns
tHDC Hold Time, CLKC to DC 100 ns
tsrc Set-Up Time, FSX or CLKX 100 ns
tHFX Hold Time, CLKx to FSx 100 ns
tozx Delay Time to Enable Dx on CL = 150 pF 125 ns
TS Entry
toox Delay Time, CLKx to Dx CL: 150 pF 125 ns
thz Delay Time, Dx to High CL: 0 pF 50 165 ns
Impedance State on TS Exit
tDTSL Delay to "r-s, Low OsCLs 150 pF 30 185 ns
tDTSH Delay to rsx Off Cr. = O pF 30 185 ns
tssx Set-Up Time, SIGx to CLKx 100 ns
tst Hold Time, CLKx to SIGx 100 ns
tSFH Set-Up Time, FSR to CLKR 100 ns
1HFR Hold Time, CLKR to FSR 100 ns
tson Set-Up Time, DR to CLKR 40 ns
trays, Hold Time, CLKR to DR 30 ns
tDSR Delay Time, CLKR to SIGR CL = 100 pF 300 ns
Timing Waveforms
TL/H/52252
YLIH/52263
CUtx .\ xzuavx /s\/T\/T\/T\_/_
ox --'1-irt"x ( x X x k, T y 7-----
TTX a -toTst "Cir""'"'"
YUM [5228-41
TUHHi22f 5
- _ [sun
--I --tHim
ILJH‘EZAIJ U
Connection Diagrams
Dual-ln-Line Package
SCI -'.
GNDA 2
A Ls ' IL. cm“
i cuun
TUPVIEW TL wszzar
Description of Pin Functions
TP3022
Pin No.
Function
Internally connected to GNDA.
Connects I/Fx to an external sample/
hold capacitor if fitted for use with pin-
compatible NMOS CODECs. Ensures
gain compatiblity.
Analog input to the encoder. This
signalwillbe sampled attheendofthe
encoder time slot and the resulting
PCM code will be shifted out during
the subsequent encode time slot.
Unused
Analog ground. All analog signals are
referenced to this pin.
Unused
Unused
Serial PCM data input to the decoder.
During the decoder time slot, PCM
data is shifted into DR, most signifi-
cant bit first, on the falling edge of
TTL output level which goes high when
the CODEC is in the power-down
mode. May be used to power-down
other circuits associated with the
PCM channel.Can bewireANDed with
other PDN outputs.
Analog output from the decoder. The
decoder sample and hold amplifier is
updated approximately 15 " after the
end of the decode time slot.
Unused
Unused
Dual-in-Line Package
TP3022 (Continued)
Pin No.
SCI- I I CLKC
SC? -.?.. al BC
VFx - - Vsa
m: " 2L st
sruuxL!., l Ele
" 2 mnza 2 an
are-h, "x! ' ___--'- Jf-ax,
PDN 2 ,..12. Vol:
vrn 2 l Th-
ncl 13 u
" i 2 GNDD
TOP VIEW TL/H15225 a
Name Function
GNDD Digitalground.A|Idigitallevelsareref-
erenced to this pin.
Dx Serial PCM TRI-STATE' output from
the encoder. During the encoder time
slot, the PCM code for the previous
sample of VFX is shifted out, most
significant bit first, on the rising edge
of CLKx.
TSX Time slot output. This TTL compatible
open-drain output pulses iow during
the encoder time slot. May be used to
enable external TRI-STATES' bus driv-
ers if highly capacitive loads must be
given. Can be wire ANDed with other
TSX outputs.
Voc 51/(s 5%) input.
CLKR Master decoder clock input used to
shift in the PCM data on DR and to
operate the decoder sequencer. May
operate at 1.536 MHz, 1.544 MHz or
2048 MHz. May be asynchronous with
CLKx or CLKc.
FSR Decoder frame sync pulse. Normally
occurring at an 8 kHz rate, this pulse is
nominally one CLKR cycle wide.
Extending the width of FSn to two or
more cycles of CLKR signifies a
receive signaling frame.
CLKx Master encoder clock input used to
shift out the PCM data on Dx and to
operate the encoder sequencer. May
operate at 1.536 MHz, 1.544 MHz or
2.048 MHz. May be asynchronous with
CLKR or CLKc.
Description of Pin Funtttions(continuem
TP3022 (Continued)
Pin No. Name Function
20 FSX Encoder frame sync pulse. Normally
occurring atan8kHzrate,this pulseis
nominally one CLKx cycle wide. Ex-
tending the width of FSx to two or
more cycles of CLKx signifies a
transmit signaling frame.
21 NC Unused
22 V38 - 5V ( t 5%) input.
23 Dc Serial control data input. Serial data
on Dc is shifted into the CODEC on the
falling edge of CLKC. In the fixed time
slot mode, Dc doubles as a power-
down input.
24 CLKC Control clockinput used to shift serial
control data into DC. CLKc must pulse
8 times during a period of time less
than or equal to one frame time, al-
though the 8 pulses may overlap a
frame boundary. CLKC need not be
synchronous with CLKX or CLKR.
Connecting CLKc continuously high
places the TP3022 into the fixed time
slot mode.
TP3023
Pin No. Name Function
1 SCI Internally connected to GNDA.
2 302 Connects I/Fx to an external sample/
hold capacitor if fitted for use with pin-
compatible NMOS CODECs. Ensures
gain compatibility.
3 VFx Analog input to the encoder. This
signal will be sampled at the end of the
encoder time slot and the resulting
PCM code will be shifted out during
the subsequent encode time slot.
4 NC Unused
5 GNDA Analog ground. All analog signals are
referenced to this pin.
6 NC Unused
7 DR Serial PCM data input to the decoder.
During the decoder time slot, PCM
data is shifted into Dm most signifi-
cant bit first, on the falling edge of
8 PDN Open drain output which turns off
when the CODEC is in the power-down
mode. May be used to power-down
other circuits associated with the
PCM channel. Can be wire ANDed with
other PDN outputs.
9 1/Fn Analog output from the decoder. The
decoder sample and hold amplifier is
updated approximately 15 us after the
end of the decode time slot.
TP3023 (Continued)
Pin No. Name Function
10 NC Unused
11 NC Unused
12 GNDD Digital ground. All digital levels are
referenced to this pin.
13 Dx Serial PCM TRI-STATES output from
the encoder. During the encoder time
slot, the PCM code for the previous
sample of I/Fx is shifted out, most
significant bit first, on the rising edge
of CLKx.
14 TSX Time slot output. This TTL compatible
open-drain output pulses low during
the encoder time slot. May be used to
enable external TRI-STATE' bus
drivers if highly capacitive loads must
be drien. Can be wire ANDed with
other TSx outputs.
15 Vcc 5V(s5%)input.
16 CLKR Master decoder clock input used to
shift in the PCM data on DR and to
operate the decoder sequencer. May
operate at 1.536 MHz, 1.544 MHz or
2.048 MHz. May be asynchronous with
CLKx or CLKc.
17 FS,, Decoder frame sync pulse. Normally
occurring at an 8 kHz rate, this pulse is
nominally one CLKH cycle wide.
18 CLKx Master encoder clock input used to
shift out the PCM data on Dx and to
operate the encoder sequencer. May
operate at 1.536 MHz 1.544 MHz, or
2.048 MHz. May be asynchronous with
CLKRorCLKC.
19 FSX Encoder frame sync pulse. Normally
occurring at an 8 kHz rate, this pulse is
nominally one CLKx cycle wide.
20 V33 - SV (25%) input.
21 DC Serial control data input. Serial data
on DcisshiftedintotheCODEConthe
falling edge of CLKc. In the fixed time
slot mode, Dc doubles as a power-
down input.
22 CLKC Control clockinput used to shift serial
control data into DC. CLKc must pulse
8 times during a period of time less
than or equal to one frame time,
although the 8 pulses may overlap a
frame boundary. CLKc need not be
synchronous with CLKx or CLKR.
Connecting CLKC continuously high
places the TP3023 into the fixed time
slot mode.
Functional Description
POWER-UP
Upon application of power, internal circuitry initializes
the CODEC and places it into the power-down mode, No
sequencing of 5V or - 5V is required. In the power-down
mode, all non-essential circuits are deactivated and the
TRI-STATE' PCM data output Dx is placed in the high im.
pedance state. Once in the power-down mode, the method
of activating the TP3022/TP3023 depends on the chosen
modeotoperation, time slot assignmentorfixedtimeslot.
TIME SLOT ASSIGNMENT MODE
.The time slot assignment mode of operation is selected
by maintaining CLKC in a normally low state. The state of
the CODEC is updated by pulsing CLKC eight times
within a period of125 its or less. The falling edge of each
clock pulse shifts the data on the DC input into the
CODEC. The first two control bits determine if the subse-
quent control bits B3-B8 are to specify the time slot for
the encoder(B1= 0), the decoder (B2 = 0) or both (Bl and
B220) or if the CODEC is to be placed into the power-
down mode (B1 and B2 = 1). The desired action will take
place upon the occurrence of the second frame sync
pulse following the first pulse of CLKC. Assigning a time
slot to either the encoder or decoder will automatically
power-up the entire CODEC circuit. The Dxoutput and DR
input, however, will be inhibited for one additional frame
to allow the analog circuitry time to stabilize. It separate
time slots are to be assigned to the encoder and the
decoder, the encoder time slot should be assigned first.
This is necessary because up to four frames are required
to assign both time slots separately, but only three
frames are necessary to activate the Dx output. it the
encode time slot has not been updated the PCM data will
be outputted during the previously assigned time slot
which may now be assigned to another CODEC.
FIXED TIME SLOT MODE
There are several ways in which the TP3022/TP3023 may
operate in the fixed time slot mode. The first and easiest
method is to leave CLKC disconnected or to connect
CLKC to Vcc. In this situation, DC behaves as a power-
down in put. When Do goes low, both encode and decode
time slots are set to one on the second subsequent frame
sync pulse. Time slot one corresponds to the eight CLKx
or CLKR cycles starting one cycle from the nominal
leading edge of FSx or FSn respectively. As in the time
slot assignment mode, the Dx output is inhibited tor one
additional frame afterthe circuit is powered up. A logical
"I'' on Dc powers the CODEC down on the second subse
quent FSx pulse.
A second fixed time slot method is to operate CLKc con-
tinuously. Placing a "I" on DC will then cause the serial
control register to fill up with ones. With BI and B2 equal
to "I'' the CODEC will power-down. Placing a "O'' on Dc
will causethe serial control registerto fill up with zeroes,
assigning time slot one to both the encoder and decoder
and powering up the device. One important restriction
with this method of operation is that the rising transition
of Dc must occur at least 8 cycles of CLKC priorto FSX. If
this restriction is not followed, it is possible that on
the frame prior to power-down, the encoder could be as-
signed to an incorrect time slot (e.g., 1, 3, 7, 15 or 31),
resulting in a possible PCM bus conflict.
SERIAL CONTROL PORT
When the TP3022/TP3023 is operated in the time slot
assignment mode or the fixed time slot mode with
continuous clock, the data on DC is shifted into the serial
control register, bit 1 first. In the time slot assignment
mode, depending on B1 and B2, the data in the RCV or
XMT time slot registers is updated at the second FSR or
FSx pulse after the first CLkc pulse, or the CODEC is
powered down. In the continuous clock fixed time slot
mode, the CODEC is powered up or down at every second
FSn or FSx pulse. The control register data is interpreted
as follows:
B1 B2 Action
0 0 Assign time slot to encoder and decoder
0 1 Assign time slot to encoder
1 0 Assign time slot to decoder
1 1 Power-down CODEC
B3 B4 B5 B6 B7 B8 Time Slot
0 0 0 0 0 O 1
0 0 0 0 0 1 2
0 0 O 0 1 0 3
0 O 0 0 1 1 4
1 1 1 1 1 0 63
1 1 1 1 1 1 64
During the power-down command, bits 3 through 8 are ig-
nored. Note that with 64 possible time slot assignments-
it is frequently possible to assign a time slot which does
not exist. This can be useful to disable an encoder or
decoder without powering down the CODEC.
ENCODING DELAY
The encoding process begins immediately at the end of
the encode time slot and is concluded no later than 17
time slots later. in normal applications, this PCM data is
not shifted out until the next time slot 125 us later,
resulting in an encoding delay of 125ps. In some applica-
tions it is possible to operate the CODEC at a higher
frame rate to reduce this delay. With a 2.048 MHz clock,
the FS rate could be increased to 15 kHz reducing the
delay from 125 its to 67 MS.
Functional Description (Continued)
DECODING DELAY
The decoding process begins immediately after the end
of the decoder time slot. The output of the decoder
sample and hold amplifier is updated 28 CLKR cycles
later. The decoding delay is therefore approximately 28
clock cycles plus one half of a frame time or 81 #5 for a
1.544 MHz system with an 8 kHz frame rate or 76 us for a
2.048 MHz system with an 8 kHz frame rate. Again, for
some applications the frame rate could be increased to
reduce this delay.
Typical Application
TYPICAL APPLICATION
A typical application of the TP3022ITP3023 used in con-
junction with the TP3040 PCM filter is shown. The values
of resistor R1 and DC blocking capacitor C1, are non'
critical. The capacitor value should exceed 0.1 “F, R1
should not exceed 160 kit. and the product R1xC1
should exceed 4 ms.
l ' m T
CLK PDN >01” VFX pun
FROM SLlC---+ VFXP vrxu ctttcr' Tsx . TSX
" I . x an
X '- SM CLK x
GSX R1 * I X CLKx
M R3 rs
50k T x '- "
A scn muzz/ x
mm .. TP3023 cLKR
A---- mar I
TO sun: ( f GNDA GNOA FSR A----
PWRU UR DR
' PWRI GNDD - M100 I
VFRO VFrd I VFR
M M Van Vcc - V V Vin, Vcc
"'cF T"" 0.1pF 0.1M:
XMTgam=20x log (9%?) +3dB
R4 _ _
RCVgain = 20 x log (m) foreach poweramplifier
.2. IE -5V
10pF 10pF
TLlH/5228-9
The power supply decoupling capacitors should be 0.1 pF. In order to take advantage of the excellent noise performance of the TP3022/TP3023/TP3040,
care must be taken in board layout to prevent coupling of digital noise into the sensitive analog lines.
. The external sample/hold capacitor required for use with pin-compatible NMOS CODECs introduces attenuation due to the capacitive divider formed
with CI. The SC? pin connects VFX to this sample/hold capacitor via a 3000 resistor to ensure gain compatibility. The TP3022/TP3023 itself does not
require an external sample/hold capacitor for proper operation.
TP3022ITP3023 Monolithic CODECs
Physical Dimensions (Continued) inches (millimeters)
l - - - fl“, - __,t
r (2319) I IIAN MAX
5 MAX (mass) GLASS
rr_lit1lTill%Llri1TslT1TslFilfraLrafrtl;
0.025 T _
m 6351 _ ' _ " _ ,
RAD ‘\
ooawms - LL! mm [11 UTE] LU ME ml (11
(0.762- I 3971
RAD TYP
0350-11420 I sd'lt/d-,. (2::
- ""I ‘I ,
(Mtlti-1triiii8) ' l MAX
_uin'n MAX F“ 0.02041 um
I4.572l f ttr5il8-C7781
ih008-ihlH2
(lhr03-iu05)
I “a TY? fl i II 0125
_ 5:0.usu I -
F - I (3.175)
mm :1170) _ F TI t MIN
MAX now own man mm mm mm
ENDS (2.5411) [2.540 0254) (0.051 .0.076)
TY? 455w“. r.
Cavity DuaI-In-Line Package (J)
Order Number TP3023J
NS Package Number J22A
fl ' oauu
-. - - 7 "ldf - - - "-l (15.24m
_rz-a-lr-asprz-o-,w-cl'Ar'snr,rortrsui-ivalrr1l, cuss
[1025 l
mvsmx\ :
RAD 'ss, flCle 52:
(13.054135)
n.mno55 (Tri-ir-ur-sro-ir-ur-nt-ni-tSLU-ri-tr
[B lii2- l, 397) -
RAD TV"
059041.5er Ihim5 cuss ”-1155 0305 T t4.572l
------ a - - - ------- -
I (1t98ii-15,748) (r135: seArANTT 1397 [1127! I (lJWl-lulN
F , (iHii18-1.7rg)
n‘oua-nmz —‘]— ‘
(il 2034.305) . ,
osas " _ _ f
1. - -i_ril6_il - -; 701mg” P am 0002 as ik12!i-th2im n.15o
vmsas (2-4391 l “'0” th01ll “”57 "”5" 9‘ (3175 5080) (3810)
1740 MAX 12.540 0.256) " _ - ' _
-t.5M mm mm
M an 5
Cavity DuaHn-Line Package (J)
Order Number TP3022J
NS Package Number J24A
LIFE SUPPORT POLICY
NATIONALS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUTTHE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONALSEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems 2. Acritical component is any component of a life support
which, (a) are intended for surgical implant into the device or system whose failure to perform can be rea-
body, or (b) support or sustain life, and whose failure to sonablyexpected to causethe failure of the life support
perform, when properly used in accordance with in- deviceor system,or to affectits safetyoreffectiveness.
structions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
u se r.
Nluonll Somlconduelnv Nllvoml Samuconduclm GmbN " Japan IClt National Semlcunduclnl Nation! Snmicnnducmos " Elcnromcs Pty. Ltd.
5gll enrpomlon Futyenne0etWasse m 5 Poe 4152 Smnluku Center Buuiumg (Mnnu Kong) Ltd, Dn 8m! Lma. Cm Smd M & Min mgnway
2900 Semtctmt1uctgr Dnve 08000 Munchen 2l l 251 Nshslurnuku, Shmwku ku lst Floor Avoa augaaeuru Fana led 830 Bayswaler. Vuclona 3153
Santa Clara, Calllurma 95051 west Germany Tokyo 160 Japan Cheung kong Electromc Bldg , ANDAR Auslvaha
Tm (408) 721 5000 Tel [089! 5 60 Ill 0 Tel mama 08H 4 Hog Yp Street 0145? Sac Paulo, Bras) Tel 03 7396333
rwx (910V 339-9240 Telex 522772 Telex 232 20‘5 NSCJ J Kwun Tang Fel ?12 " Telex 32096
F,0wtgn. Hong Kong Telex H3931 NSBR
Tel 31339233
Telex 438bh NSEHK "
Cable NATSEMI Hr
Nallonal Mes no! assume any responsrthlrlt fov use ul any Lucumy assumed JO LIICU" paler“ menses ave ‘mpheu ano Nahonm veserves me ngnl al any hme wwlhoul nohce lo change said wcuvlly
This datasheet has been :
www.ic-phoenix.com
Datasheets for electronic components.
National Semiconductor was acquired by Texas Instruments.
corp/docs/irwestor_relations/Pr_09_23_201 1_national_semiconductor.html
This file is the datasheet for the following electronic components:
TP3023J - product/tp3023j?HQS=TI-null-nu|I-dscatalog-df-pf-null-wwe
TP3022J - product/tp3022j?HQS=T|—null-nu|I-dscatalog-df-pf-nuII-wwe
