TP3021J-1 ,MONOLITHIC CODECSBlock Diagram
CLKI
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CL!"
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TP3023J ,7V, monolithic CODECElectrical Characteristics Unless otherwise anéa TA = 0''C to 70°9ch = 5.0V t 5%, Visss = - 5.0V t ..
TP3040AJ ,TP3040/ TP3040A PCM Monolithic FilterFeaturesYDesigned for D3/D4 and CCITT
TP3040AN ,TP3040/ TP3040A PCM Monolithic FilterFeaturesYDesigned for D3/D4 and CCITT
TP3040J ,TP3040/ TP3040A PCM Monolithic FilterTP3040,TP3040APCMMonolithicFilterSeptember1994TP3040,TP3040APCMMonolithicFilterGeneralDescription
TP3040V ,TP3040/ TP3040A PCM Monolithic FilterTP3040,TP3040APCMMonolithicFilterSeptember1994TP3040,TP3040APCMMonolithicFilterGeneralDescription
TPSV107K025R0100 , Low ESR series of robust Mn02 solid electrolyte capacitors
TPSV477M010R0060 , 60-A, 3.3/5-V INPUT, NONISOLATED WIDE-OUTPUT ADJUST POWER MODULE
TPSW226K016R0500 , TPS Series Low ESR
TPSX107K010R0150 , Low ESR series of robust Mn02 solid electrolyte capacitors
TPU3040 , Teletext Processors
TQ2-3V , 2-pole 5 mm Surface Mount Relay, JIS C0806 compliant Measurement equipment
TP3020J-TP3020J-1-TP3021J-TP3021J-1
MONOLITHIC CODECS
I National
_ Semiconductor
TP3020, TP3020-1, TP3021, TP3021-1
Monolithic CODECs
General Description
The TP3020 and TP3021 are monolithic PCM CODECs im-
plemented with double-poly CMOS technology. The TP3020
is intended for p-law applications and contains logic for p.-
law signaling insertion and extraction. The TP3021 is intend-
ed for A-law applications.
Each device contains separate OM and A/D circuitry, all
necessary sample and hold capacitors, a precision voltage
reference and internal auto-zero circuit. A serial control port
allows an external controller to individually assign the PCM
input and output ports to one of up to 32 time slots or to
place the CODEC into a power-down mode. Alternately, the
TP3020/TP3021 may be operated in a fixed time slot mode.
Both devices are intended to be used with the TP3040
monolithic PCM filter which provides the input anti-aliasing
function for the encoder and smoothes the output of the
decoder and corrects for the sin x/x distortion introduced by
the decoder sample and hold output.
Featu res
I: Low operation power-45 mW typical
ll Low standby power-I mW typical
:1 t5V operation
I: TTL compatible digital interface
ll Time slot assignment or alternate fixed time slot modes
" Internal precision reference
I: Internal sample and hold capacitors
ll Internal auto-zero circuit
I: TP302H-law coding with signaling capabilities
" TP3021--Nlaw coding
ll Synchronous or asynchronous operation
Simplified Block Diagram
"X mull]?! HOLD
AUTOAZEIIO
COUPARAI’OR
ML! AND HOLD
95x W III."
Ctmrtttrk cu;
ttht mam "tel
- 5.0V
TL/H/5538-1
L-LZOSdJ. ‘lZOSdJ. 'L'OZOSdJ. ‘OZOSdl
TP3020, TP3020-1, TP3021, TP3021-1
Connection Diagrams
Dual-ln-Line Package
w u, U lcuc
Mt 2 ll. o;
"x 2 , Vu
me A Sl. m,
m n.» 2 st. "x
nan 2 1 cu,
" 2 ll. n“
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Vin ‘J. 1 ii;
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TLfH/5538-3
Top View
Order Number TP3020J or TP3020J-1
See NS Package Number J24A
Description of Pin Functions
Symbol
Function
Internally connected to GNDA.
Connects VFx to an external sample/hold capaci-
tor it fitted for use with pin-compatible NMOS CO-
DECs. Ensures gain compatibility.
Analog input to the encoder. This signal will be
sampled at the end of the encoder time slot and
the resulting PCM code will be shifted out during
the subsequent encode time slot.
Analog and digital ground. All analog and digital
signals are referenced to this pin.
Receive signaling bit output. During receive signal-
ing frames the least significant (last) bit shifted into
DR is internally latched and appears at this out-
put-SOR will then remain valid until changed dur-
ing a subsequent receive signaling frame or reset
by a power-down command.
Serial PCM data input to the decoder. During the
decoder time slot, POM data is shifted into the,
most significant bit first, on the falling edge of
TTL output level which goes high when the co-
DEC is in the power-down mode. May be used to
power-down other circuits associated with the
PCM channel.
Analog output from the decoder. The decoder
sample and hold amplifier is updated approximate-
ly 15 ps after the end of the decode time slot.
Symbol
Dual-ln-Llne Package
set l I -ttttt
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TL/H/5536-4
Top View
Order Number TP302td or TP3021J-1
See NS Package Number J22A
Function
Unused
Serial PCM TRl-STATE0 output from the encoder.
During the encoder time slot, the PCM code for the
previous sample of VFx is shifted out, most signifi-
cant bit first, on the rising edge of CLKX.
Time slot output. This TTL compatible open-drain
output pulses low during the encoder time slot.
May be used to enable external TRI-STATE bus
drivers if highly capacitive loads must be driven.
Can be wire ANDed with other t%x outputs.
5V (15%) Power Supply.
Master decoder clock input used to shift in the
PCM data on DR and to operate the decoder se-
quencer. May operate at 1.536 MHZ. 1.544 MH, or
2048 MHz. May be asynchronous with CLKx or
Decoder frame sync pulse. Normally occurring at
an 8 kHz rate, this pulse is nominally one CLKR
cycle wide. Extending the width of FSR to two or
more cycles of CLKR signifies a receive signaling
frame.
Master encoder clock input used to shift out the
PCM data on Dx and to operate the encoder se-
quencer. May operate at 1.536 MHz, 1.544 MHz or
2.048 MHz. May be asynchronous with CLKR or
Encoder frame sync pulse. Normally occurring at
an 8 kHz rate, this pulse is nominally one CLKx
cycle wide. Extending the width of PBX to two or
more cycles of CLKx signifies a transmit signaling
frame.
Description of Pin Functions (Continued)
Symbol Functlon
SlGx Transmit signaling input. During a transmit signal-
ing frame, the signal at SlGx is shifted out of Dx in
place of the least significant (last) bit of PCM data.
Vas --5V (15%) input,
Dc Serial control data input. Serial data on Dc is shift-
ed into the CODEC on the falling edge of CLKc. In
the fixed time slot mode, Dc doubles as a power-
down input.
Absolute Maximum Ratings
Operating Temperature -25% to + 125°C
Storage Temperature -65''C to + 150'C
Vcc with Respect to GND 7V
Visit with Respect to GND -7V
ESD rating is to be determined.
DC Electrical Characteristics
Function
Control clock input used to shift serial control data
into Dc. CLKc must pulse 8 times during a period
of time less than or equal to one frame time, al-
though the 8 pulses may overlap a frame bounda-
ry. CLKC need not be synchronous with CLKx or
CLKR. Connecting CLKC continuously high places
the TP3020/TP3021 into the fixed time slot mode.
Symbol
Voltage at Any Analog
Input or Output V33 - 0.3V to Vcc + 0.3V
Voltage at Any Digital
Input or Output GND-0.3V to Vcc + 0.3V
Lead Temperature
(Soldering, 10 seconds) 300'C
Unless otherwise noted, limits printed in BOLD characters are guaranteed for Vcc = + 5.0V : 5%, V33 = - 5.0V 1 5%; TA =
0°C to 70'C by correlation with 100% electrical testing at TA == 25°C. All other limits are assured by correlation with other
production tests and/or product design and characterization. All signals referenced to GND. Typicals sptscifiad at Vcc =
+5.OV, VBB = --5.0V and TA = 25°C.
Symbol Parameter Conditions I Min I Typ Max l Units
DIGITAL INTERFACE
ll Input Current 0
VIL Input Low Voltage 0.6 V
VIH Input High Voltage " V
VOL Output Low Voltage Dx, lot. = 4.0 mA 0.4 V
SIGR, IOL= 0.5 mA 0.4 V
TSX, lot. = 3.2 mA, Open Drain 0.4 V
PDN, loL= 1.6 mA 0.4 V
VOH Output High Voltage Dy. 10H = 6 mA 2.4 V
SIGR, I0H=0.6 mA 2.4 V
ANALOG INTERFACE
A VFx Input Impedance when Resistance in Series with 2.0 kit
Sampling Approximately 70 pF
20 Output impedance at VFR - 3.1V Vos Output Offset Voltage at VFR DR = PCM Zero Code (T P3020) - " " mV
or Alternating i 1 Code (T P3021)
lm Analog Input Bias Current VIN = 0V - 0.1 0.1 ,uA
R1 M C1 DC Blocking Time Constant 4.0 ms
C1 DC Blocking Capacitor 0.1 pF
R1 Input Bias Resistor 160 ktt
POWER DISSIPATION
loco Standby Current, Vcc 0.1 0.4 mA
I330 Standby Current, V35 0.03 o. 1 mA
Iccl Operating Current, Vcc 4.5 tho mA
lBB1 Operating Current, V33 4.5 tho mA
l-‘lZOSdJ. 'lZOSdJ. i|-'0308d.l. 'OZOSdJ.
TP3020, TP3020-1, TP3021, TP3021-1
AC Electrical Characteristics
Unless otherwise noted, the analog input is a 0 dBm0, 1.02 kHz sine wave. The digital input is a PCM bit stream generated by
passing a 0 dBmO, 1.02 kHz sine wave through an ideal encoder. All output levels are sin x/x corrected. Limits printed in BOLD
characters are guaranteed for Vcc = +5V 325%, V55 = -5V 1 5%; TA = 0°C to + 70'C by correlation with 100% electrical
testing at TA = 25''C. All other limits are assured by correlation with other production tests andlor product design and character-
ization. All signals referenced to GND. Typicals specified at Vcc = +5V, V33 = --51t, TA = 25''C.
Symbol Parameter Conditions Min Typ Max Units
Absolute Level The nominal 0 dBmO levels for
the TP3020 and TP3021 are
1.520 Vrms and 1.525 Vrms
respectively. The resulting
nominal overload level is 3.096V
peak for both devices. All gain
measurements for the encode
and decode portions of the
TP3020/TP3021 are based on
these nominal levels after the
necessary sin x/x corrections are
GRA Receive Gain, Absolute T---25''C, VCC= 5V, VBB= -5V
TP3020, TP3021 -thf2S 0.125 dB
TP3020-1,TP3021-1 -ttATS 0.175 dB
GRAT Absolute Receive Gain T= 0°C to 70°C -0.05 0.05 dB
Variation with Temperature
GRAV Absolute Receive Gain Vcc = 5V i 5%, - 0.07 0.07 dB
Variation with Supply Voltage Var-- - 5V , 5%
GXA Transmit Gain, Absolute T = 25''C, Vcc = 5V, V93 = - 5V
TP3020, TP3021 - 0.325 - 0.075 dB
TP3020-1, TP3021-1 - 0.375 - 0.025 dB
GXAT Absolute Transmit Gain T = 0°C to 70"C -0.05 0.05 dB
Variation with Temperature
GXAV Absolute Transmit Gain Vcc = 5V i 5%, - 0.07 0.07 dB
Variation with Supply Voltage VBB= - 5V i 5%
GRAL Absolute Receive Gain CCITT Method 2 Relative
Variation with Level to --10 dBmO
0 dBmO to 3 dBmO -0.a 0.3 dB
-40 dBmO to 0 dBmO - 0.2 0.2 dB
-50 dBmo to -40 dBmO -tt.q 0.4 dB
-55 dBmO to -50 dBmo -1.0 1.0 dB
GxAL Absolute Transmit Gain CCITT Method 2 Relative
Variation with Level to - 10 dBmo
0 dBmO to 3 dBmO -o.a 0.3 dB
-40 dBmo to 0 dBmo - 0.2 0.2 dB
-50 dBmO to -40 dBmo -thq 0.4 dB
-55 dBmo to -50 dBmo - 1.0 1.0 dB
S/DR Receive Signal to Distortion Sinusoidal Test Method Input
Ratio Level
-30 dBmO to 0 dBmO " dBc
-40 dBmO " dBc
--45 dBmO " dBc
S/D, Transmit Signal to Distortion Sinusoidal Test Method Input
Ratio Level
-30 dBmO to o dBmO att dBc
-40 dBmo " dBc
- 45 d Bm0 2 5 dBc
NR Receive Idle Channel Noise DR = Steady State PCM Code tt dBch
N, Transmit idle Channel Noise TP3020, (No Signaling) 1 a dBch
TP3021 (Note 1) -Btp dBnOp
HDR Receive Harmonic Distortion 2nd or 3rd Harmonic - " dB
HD, Transmit Harmonic Distortion 2nd or 3rd Harmonic - " dB
PPSRx Positive Power Supply Input Level = OV, Vcc = 5.0 Voc so dB
Rejection. Transmit
+ 300 mVrms, t= 1.02 kHz
Note r. Measured by extrapolation from the distortion test result at - 50 dBm level.
AC Electrical Characteristics (Continued)
Unless otherwise noted, the analog input is a 0 dBmo, 1.02 kHz sine wave. The digital input is a PCM bit stream generated by
passing a 0 dBmo, 1.02 kHz sine wave through an ideal encoder. All output levels are sin x/x corrected. Limits printed in BOLD
characters are guaranteed for Vcc = +5V 15%, V35 = -5V i5%; TA = 0'C to +70°C by correlation with 100% electrical
testing at TA = 25''C. All other limits are assured by correlation with other production tests and/ or product design and character-
ization. All signals referenced to GND. Typicals specified at VCC = +5V, V35 = -5V, TA == 25''C.
Symbol Parameter Conditions Min Typ Max Unlts
PPSRR Positive Power Supply Dn = Steady PCM Code, 40 dB
Rejection, Receive Vcc = 5.0 VDC + 300 mes,
F = 1.02 kHz
NPSRX Negative Power Supply Input Level = 0V, V33 = - 5.0 VDC so dB
Rejection. Transmit + 300 mVrms, =1.02 kHz
NPSRR Negative Power Supply OR = Steady PCM Code, " dB
Rejection, Receive V83 = -5.0 VDC + 300 mVrms,
1= =1.02 kHz
CTXR Transmit to Receive Crosstalk DR = Steady PCM Code - " dB
CTRX Receive to Transmit Crosstalk Transmit Input Level = 0V
TP3020 - TO dB
TP3021 - 65 (Note 2) dB
Note 2: Theoretical worst-case for a perfectly zeroed encoder with alternating sign bit, due to the decoding law.
Timing Specification Unless otherwise noted, limits printed in BOLD characters are guaranteed for Vcc = + SV
15%, V33 = -5V i5%: TA = 0°C to 70'C by correlation with 100% electrical testing at TA = 25°C. All other limits are
assured by correlation with other production tests and/or product design and characterization. All digital signals referenced to
GND. Typicals specified at VCC = + 5V, Vim = -5V, TA = 25°C. All timing parameters are measured at VOH = 2.0V and VOL
L'lZOSdJ. 'l-ZOSdJ. 'l'OZOSdJ. ‘OZOSdJ.
= 0.7V.
Symbol Parameter Condltlons Mln Typ Max Unlts
tpc Period of Clock CLKC, CLKR, CLKx 485 ns
tnc, th Rise and Fall Time of Clock CLKC, CLKR, CLKx 30 ns
tWCH Width of Clock High CLKO CLKR, CLKx 1 65 ns
mm Width ot Clock Low CLKc. CLKR, CLKx 165 ns
tA/D Al D Conversion Time From End of Encoder Time 1 It Time
Slot to Completion of Slots
Conversion
tD/A D/A Conversion Time From End of Decoder Time 2 Time
Slot to Transition of VFn Slots
ISDC Set-Up Time, Do to CLKC 1 00 ns
tHDC Hold Time, CLKC to DC 100 ns
tSFX Set-Up Time, FSX to CLKx 100 ns
tHFx Hold Time, CLKx to FSX 1 oo ns
tsz Delay Time to Enable Dx on CL: 150 pF 25 125 ns
TS Entry
tDDx Delay Time, CLKX to Dx CL = 150 pF 1 " ns
th2 Delay Time, Dx to High CL = 0 pF 50 165 ns
Impedance State on TS Exit
tDTSL Delay to T-s, Low 0 s; CL s 150 pF 30 185 ns
tDTSH Delay to Tgx Off CL-- 0 pF 30 185 ns
tssx Set-Up Time, SlGx to CLKx 100 ns
:st Hold Time, CLKx to SIG)( 100 ns
tsrn Set-Up Time, FSR to CLKR too ns
tHFR Hold Time, CLKR to FSn 100 ns
ISDR Set-Up Time, DR to CLKR 40 ns
tHDR Hold Time, CLKR to DR att ns
tDSR Delay Time, CLKR to SIGH Cr. =100 pF 300 ns
TP3020, TP3020-1, TP3021, TP3021-1
Timing Waveforms
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ei?, t1'il
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(mm ONLY)
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TL/H15538-2
Functional Description
POWER-UP
Upon application of power, internal circuitry initializes the
CODEC and places it into the power-down mode. No se-
quencing of 5V or -5V is required. In the power-down
mode, all non-essential circuits are deactivated, the TRI.
STATE PCM data output Dx is placed in the high impedance
state and the receive signaling output of the TP3020, SIGR,
is reset to logical zero. Once in the power-down mode, the
method of activating the TP3020/TP3021 depends on the
chosen mode of operation, time slot assignment or fixed
time slot.
TIME SLOT ASSIGNMENT MODE
The time slot assignment mode of operation is selected by
maintaining CLKC in a normally low state. The state of the
CODEC is updated by pulsing CLKC eight times within a
period of 125 us or less. The falling edge of each clock
pulse shifts the data on the DC input into the CODEC. The
first two control bits determine if the subsequent control bits
B3-B8 are to specify the time slot for the encoder (B1 = O),
the decoder (82:0) or both (BI and 82:0) or if the CO-
DEC is to be placed into the power-down mode (B1 and
32: 1). The desired action will take place upon the occur-
rence of the second frame sync pulse following the first
pulse of CLKC. Assigning a time slot to either the encoder or
decoder will automatically power-up the entire CODEC cir-
cuit. The Dx output and DR input, however, will be inhibited
for one additional frame to allow the analog circuitry time to
stabilize. If separate time slots are to be assigned to the
encoder and the decoder, the encoder time slot should be
assigned first. This is necessary because up to four frames
are required to assign both time slots separately, but only
three frames are necessary to activate the Dx output. It the
encode time slot has not been updated the PCM data will be
outputted during the previously assigned time slot which
may now be assigned to another CODEC.
FIXED TIME SLOT MODE
There are several ways in which the TP3020/TP3021 may
operate in the fixed time slot mode. The first and easiest
method is to leave CLKC disconnected or to connect CLKC
to VCC- In this situation, DC behaves as a power-down input.
When DC goes low, both encode and decode time slots are
set to one on the second subsequent frame sync pulse.
Time slot one corresponds to the eight CLKx or CLKH cy-
cles starting one cycle from the nominal leading edge of
FSx or FSR respectively. As in the time slot assignment
mode, the Dx output is inhibited for one additional frame
after the circuit is powered up. A logical "1" on Dc powers
the CODEC down on the second subsequent FSX pulse.
A second fixed time slot method is to operate CLKC continu-
ously. Placing a "I '' on DC will then cause the serial control
register to fill up with ones. With Bl and B2 equal to "I '' the
CODEC will power-down. Placing a "o" on Dc will cause the
serial control register to fill up with zeroes. assigning time
slot one to both the encoder and decoder and powering up
the device. One important restriction with this method of
operation is that the rising transition of DC must occur at
least 8 cycles of CLK.3 priorto FSX. If this restriction is not for.
lowed, it is possible that on the frame prior to power-down,
the encoder could be assigned to an incorrect time slot
(e.g., I, 3, 7, 15 or 31), resulting in a possible PCM bus
conflict.
SERIAL CONTROL PORT
When the TP3020/TP3021 is operated in the time slot as-
signment mode or the fixed time slot mode with continuous
clock, the data on Dc is shifted into the serial control regis-
ter, bit 1 first. In the time slot assignment mode, depending
on B1 and B2, the data in the RCV or XMT time slot regis-
ters is updated at the second FSR or FSx pulse after the
first CLKC pulse, or the CODEC is powered down. In the
continuous clock fixed time slot mode, the CODEC is pow-
ered up or down at every second FSR or FSX pulse. The
control register data is interpreted as follows:
B1 B2 Action
0 0 Assign time slot to encoder and decoder
0 1 Assign time slot to encoder
1 0 Assign time slot to decoder
1 1 Power-down CODEC
B3 B4 B5 B6 B7 B8 Tlme Slot
0 o 0 0 0 O 1
0 o 0 0 0 1 2
0 O 0 0 1 0 3
0 0 O 0 1 1 4
1 1 1 1 1 0 63
1 1 1 1 1 1 64
During the power-down command, bits 3 through 8 are ig-
nored. Note that with 64 possible time slot assignments it is
frequently possible to assign a time slot which does not
exist. This can be useiul to disable an encoder or decoder
without powering down the CODEC.
SIGNALING
The TP3020 p-law CODEC contains circuitry to insert and
extract signaling information for the PCM data. The transmit
signaling frame is signified by widening the FSx pulse from
one cycle of CLKX to two or more cycles
When this occurs, the data present on the SIGx input at the
eighth clock pulse of the encode time slot is inserted into
the last bit of the PCM data stream. A receive signaling
frame is indicated in a similar fashion by widening the FSR
pulse to two or more cycles of CLKR.
During a receive signaling frame, the last PCM bit shifted in
is latched into a flip-flop and appears at the SIGR output.
This output will remain unchanged until the next signaling
frame, until a power-down is executed or until power is re-
moved from the device. Since the least significant bit of the
PCM data is lost during a signaling frame, the decoder inter-
prets the bit as a "Yi'' (i.e., half way between a "o"
and a "I''). This minimizes the noise and distortion due to
the signaling.
l-LZOSdJ. ‘tZOEdJ. ‘L-ozoccu. ‘ozoedJ.
TP3020, TP3020-1, TP3021, TP3021-1
Functional Description (Continued)
ENCODING DELAY
The encoding process begins at the start of the encode time
slot and is concluded no later than 17 time slots later, In
normal applications, this PCM data is not shifted out until
the next time slot 125 us later, resulting in an encoding
delay of 125 us. In some applications it is possible to oper-
ate the CODEC at a higher frame rate to reduce this delay.
With a 2.048 MHz clock, the FS rate could be increased to
15 kHz reducing the delay from 125 p8 to 67 pS.
DECODING DELAY
The decoding process begins immediately after the end of
the decoder time slot. The output of the decoder sample
and hold amplifier is updated 28 CLKR cycles later.
Typical Application
The decoding delay is therefore approximately 28 clock cy-
cles plus one half of a frame time or 81 pS for a 1.544 MHz
system with an 8 kHz frame rate or 76 us for a 2.048 MHz
system with an 8 kHz frame rate. Again, for some applica-
tions the frame rate could be increased to reduce this delay.
TYPICAL APPLICATION
A typical application of the TP3020/TP3021 used in con-
junction with the TP3040 PCM filter is shown. The values of
resistor R1 and DC blocking capacitor C1. are non-critical.
The capacitor value should exceed 0.1 pF, RI should not
exceed 160 kn, and the product R1 M CI should exceed 4
rms. 0.1 pf power supply bypass capacitors should be used
and placed as close to the device as possible.
ClK run >0.1 " vrx mi
mom 'tle-----) Vin‘ wxo " Cttcr' th wir,
"xt- T" 362 ttx W0tt
ssx :J. tutr (:le
m R3 JI "T" rsx g: rsx
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vrao Wal 6 VFn
'u M Van Ittt Tr V Vac ltet
'"'tt MMF OJ " 0-1 "
E J, +5v
J. k -w
as + R2 "vi::, Emir
XMTgain = 20 \' Iog( )+ 3d8
RCV gain = 20 x log ( R4 tot each power ampiiier
R2 + R5
TL/H/5538-5
The power supply decoupling capacitors should be 0.1 pF. In order to take advantage of the excellent noise performance of the TP3020/TP3021/TP3040. care
must be taken in board layout to prevent coupling of digital noise into the sensitive analog lines.
'The external sample/hoid capacitor required tor use with pin-compatible NMOS CODECs Introduces attenuation due to the capacitive divider formed with C1. The
SC pin connects VFx to this sample/hold capacitor (via a 300n resistor) to ensure gain compatibility. The TP3020/TP3021 itseii does not require an extemai
sampie/hold capaciton
This datasheet has been :
www.ic-phoenix.com
Datasheets for electronic components.
National Semiconductor was acquired by Texas Instruments.
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This file is the datasheet for the following electronic components:
TP3021-1 - product/tp3021-1?HQS=TI-nu|I-nu|I-dscataIog-df-pf-nulI-wwe
TP3020J-1 - product/tp3020j-1?HQS=TI-nulI-nu|I-dscatalog-df-pf—nuII-wwe
TP3020 - product/tp3020?HQS=T|-nu|I-null-dscatalog-df—pf—nuII-wwe
TP3021J - product/tp3021j?HQS=TI-nuII-nu|I-dscatalog-df-pf-nulI-wwe
TP3020-1 - product/tp3020-1?HQS=TI-nu|I-nu|I-dscataIog-df-pf-nulI-wwe
TP3021J-1 - product/tp3021j-1?HQS=TI-nulI-nu|I-dscatalog-df-pf—nuII-wwe
TP3020J - product/tp3020j?HQS=T|—null-nu|I-dscatalog-df-pf-nuII-wwe
TP3020J-1 - product/tp3020j—1?HQS=T|-nu|I-nuII-dscatalog-df-pf-nuII-wwe
TP3020 - product/tp3020?HQS=T|-nu|l-null-dscatalog-df—pf—nuII-wwe
TP3020-1 - product/tp3020-1?HQS=T|-nu|I-nulI-dscataIog-df—pf—nulI-wwe
TP3020J - product/tp3020j?HQS=T|—null-nu|I-dscatalog-df—pf-nuII-wwe
TP3021J-1 - product/tp3021j—1?HQS=TI-nu|I-null-dscatalog-df—pf—nuII-wwe
TP3021-1 - product/tp3021-1?HQS=T|-nu|I-nu|I-dscataIog-df—pf—null-wwe
TP3021J - product/tp3021j?HQS=T|—null-nu|I-dscatalog-df-pf-nuII-wwe
