TMS32C6416EGLZ6E3 ,Fixed-Point Digital Signal Processormaximum ratings over operating caseGLZ, ZLZ and CLZ BGA packages (bottom view) . . . . . . . . 3tem ..
TMS32C6416EGLZ7E3 ,Fixed-Point Digital Signal ProcessorFeatures− Serial Peripheral Interface (SPI)− Byte-Addressable (8-/16-/32-/64-Bit Data)Compatible ..
TMS32C6416EGLZA5E0 ,Fixed-Point Digital Signal ProcessorFeatures− Serial Peripheral Interface (SPI)− Byte-Addressable (8-/16-/32-/64-Bit Data)Compatible ..
TMS32C6416EGLZA6E3 ,Fixed-Point Digital Signal ProcessorTMS320C6414, TMS320C6415, TMS320C6416FIXED-POINT DIGITAL SIGNAL PROCESSORSSPRS146N − FEBRUARY 2001 ..
TMS32C6711BGFNA100 ,Floating-Point DSP [Revision D Recommended for New Designs]
TMS32C6713BGDPA200 ,Floating-Point Digital Signal Processormaximum ratings over operating casedevice characteristics . . . . . . . . . . . . . . . . . . . . . ..
TPS61045DRBR ,28-V, 85% Efficient Boost Converter in QFN-8 for LCD ApplicationsElectrical Characteristics....... 511.2 Trademarks..... 186.7 Typical Characteristics. 611.3 Electr ..
TPS61045DRBR G4 ,28-V, 85% Efficient Boost Converter in QFN-8, Digitally Adjustable 8-SON -40 to 85Block Diagram..... 8Information..... 184 Revision HistoryChanges from Revision B (March 2009) to Re ..
TPS61045DRBRG4 ,28-V, 85% Efficient Boost Converter in QFN-8, Digitally Adjustable 8-SON -40 to 85Maximum Ratings(1)over operating free-air temperature (unless otherwise noted)MIN MAX UNIT(2)Supply ..
TPS61045DRBRG4 ,28-V, 85% Efficient Boost Converter in QFN-8, Digitally Adjustable 8-SON -40 to 85Maximum Ratings . 410.1 Layout Guidelines.... 176.2 ESD Ratings........ 410.2 Layout Example....... ..
TPS61045DRBT ,28-V, 85% Efficient Boost Converter in QFN-8 for LCD ApplicationsFeatures... 17.4 Device Functional Modes.... 102 Applications..... 18 Application and Implementatio ..
TPS61050DRCR ,1.2A High Power White LED Driver with I2C Compatible Interface 10-VSON -40 to 85Features 3 DescriptionThe TPS6105x device is based on a high-frequency1• Four Operational Modessync ..
TMS32C6416DGLZA5E0-TMS32C6416EGLZ5E0-TMS32C6416EGLZ6E3-TMS32C6416EGLZ7E3-TMS32C6416EGLZA5E0-TMS32C6416EGLZA6E3
Fixed-Point Digital Signal Processor
− Twenty-Eight Operations/Cycle− 4000, 4800, 5760 MIPS − Fully Software-Compatible With C62x™− C6414/15/16 Devices Pin-Compatible VelociTI.2™ Extensions to VelociTI™Advanced Very-Long-Instruction-Word(VLIW) TMS320C64x™ DSP Core − Eight Highly Independent FunctionalUnits With VelociTI.2™ Extensions: − Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad8-Bit Arithmetic per Clock Cycle− Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle orEight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle− Non-Aligned Load-Store Architecture− 64 32-Bit General-Purpose Registers − Instruction Packing Reduces Code Size− All Instructions Conditional Instruction Set Features − Byte-Addressable (8-/16-/32-/64-Bit Data)− 8-Bit Overflow Protection− Bit-Field Extract, Set, Clear − Normalization, Saturation, Bit-Counting− VelociTI.2™ Increased Orthogonality Viterbi Decoder Coprocessor (VCP) [C6416]− Supports Over 600 7.95-Kbps AMR − Programmable Code Parameters Turbo Decoder Coprocessor (TCP) [C6416]− Supports up to 7 2-Mbps or 43 384-Kbps 3GPP (6 Iterations)− Programmable Turbo Code andDecoding Parameters L1/L2 Memory Architecture − 128K-Bit (16K-Byte) L1P Program Cache(Direct Mapped) − 128K-Bit (16K-Byte) L1D Data Cache(2-Way Set-Associative) − 8M-Bit (1024K-Byte) L2 Unified MappedSBSRAM, ZBT SRAM, and FIFO) − 1280M-Byte Total Addressable ExternalMemory Space Enhanced Direct-Memory-Access (EDMA)Controller (64 Independent Channels) Host-Port Interface (HPI) − User-Configurable Bus Width (32-/16-Bit) 32-Bit/33-MHz, 3.3-V PCI Master/SlaveInterface Conforms to PCI Specification 2.2[C6415/C6416 ] − Three PCI Bus Address Registers:Prefetchable Memory Non-Prefetchable Memory I/O− Four-Wire Serial EEPROM Interface− PCI Interrupt Request Under DSPProgram Control − DSP Interrupt Via PCI I/O Cycle Three Multichannel Buffered Serial Ports− Direct I/F to T1/E1, MVIP, SCSA Framers− Up to 256 Channels Each − ST-Bus-Switching-, AC97-Compatible− Serial Peripheral Interface (SPI)Compatible (Motorola™) Three 32-Bit General-Purpose Timers Universal Test and Operations PHY Interface for ATM (UTOPIA) [C6415/C6416]− UTOPIA Level 2 Slave ATM Controller− 8-Bit Transmit and Receive Operationsup to 50 MHz per Direction − User-Defined Cell Format up to 64 Bytes Sixteen General-Purpose I/O (GPIO) Pins Flexible PLL Clock Generator IEEE-1149.1 (JTAG†) Boundary-Scan-Compatible 532-Pin Ball Grid Array (BGA) Package(GLZ, ZLZ and CLZ Suffixes), 0.8-mm BallPitch 0.13-µm/6-Level Cu Metal Process (CMOS) 3.3-V I/Os, 1.2-V/1.25-V Internal (500 MHz) 3.3-V I/Os, 1.4-V Internal (600 and 720 MHz) Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
C62x, VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
