TMS320VC549PGE-100 ,Digital Signal ProcessorElectrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 13 Serial Port Receive Timin ..
TMS320VC549PGE-100 ,Digital Signal ProcessorElectrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 13 Serial Port Receive Timin ..
TMS320VC549PGE120 ,Digital Signal Processor SPRS078G − SEPTEMBER 1998 − REVISED OCTOBER 2004 Advance ..
TMS320VC549PGE-120 ,Digital Signal ProcessorElectrical Characteristics Over Recommended Operating Case Temperature Range table:I , Supply curre ..
TMS320VC549PGE80 ,Digital Signal ProcessorFeatures:Deleted “(Product Preview Data)” from the “8.3-ns Single-Cycle Fixed-Point Instruction Exe ..
TMS320VC549PGE-80 ,Digital Signal ProcessorMaximum Ratings . . . . . . . . . . . . . . . . . . . . 12 HOLD and HOLDA Timing . . . . . . . . . ..
TPS61025DRCR ,3.3-V Output, 1.5-A Switch, 96% Efficient Boost Converter w/ LDO Down-Mode, QFN-10 SLVS451G–SEPTEMBER 2003–REVISED DECEMBER 20146 Device Comparison Table(1) (2)T OUTPUT VOLTAGE DC-D ..
TPS61025DRCRG4 ,3.3-V Output, 1.5-A Switch, 96% Efficient Boost Converter w/ LDO Down-Mode, QFN-10 10-VSON -40 to 85Features 3 DescriptionThe TPS6102x family of devices provide a power1• 96% Efficient Synchronous Bo ..
TPS61026DRCR ,5.0-V Output, 1.8-A Switch, 96% Efficient Boost Converter w/ LDO Down-Mode, QFN-10 10-VSON -40 to 85Features 3 DescriptionThe TPS6102x family of devices provide a power1• 96% Efficient Synchronous Bo ..
TPS61026DRCT ,5.0-V Output, 1.8-A Switch, 96% Efficient Boost Converter w/ LDO Down-Mode, QFN-10 10-VSON -40 to 85 SLVS451G–SEPTEMBER 2003–REVISED DECEMBER 20146 Device Comparison Table(1) (2)T OUTPUT VOLTAGE DC-D ..
TPS61027DRC , 96% EFFICIENT SYNCHRONOUS BOOST CONVERTER WITH 1.5-A SWITCH
TPS61027DRCR ,5-V Output, 1.5-A Switch, 96% Efficient Boost Converter w/ LDO Down-Mode, QFN-10Features... 110.5 Programming... 122 Applications..... 111 Application and Implementation...... 143 ..
TMS320VC549GGU-120-TMS320VC549PGE100-TMS320VC549PGE-100-TMS320VC549PGE120-TMS320VC549PGE-120-TMS320VC549PGE80-TMS320VC549PGE-80
Digital Signal Processor
Independent 40-Bit Accumulators 17- × 17-Bit Parallel Multiplier Coupled to a
40-Bit Dedicated Adder for Non-Pipelined
Single-Cycle Multiply/Accumulate (MAC)
Operation Compare, Select, and Store Unit (CSSU) for
the Add/Compare Selection of the Viterbi
Operator Exponent Encoder to Compute an
Exponent Value of a 40-Bit Accumulator
Value in a Single Cycle Two Address Generators With Eight
Auxiliary Registers and Two Auxiliary
Register Arithmetic Units (ARAUs) Data Bus With a Bus Holder Feature Address Bus With a Bus Holder Feature Extended Addressing Mode for 8M × 16-Bit
Maximum Addressable External Program
Space 192K × 16-Bit Maximum Addressable
Memory Space (64K Words Program,
64K Words Data, and 64K Words I/O) On-Chip ROM with Some Configurable to
Program/Data Memory Dual-Access On-Chip RAM Single-Access On-Chip RAM Single-Instruction Repeat and
Block-Repeat Operations for Program Code Block-Memory-Move Instructions for Better
Program and Data Management Instructions With a 32-Bit Long Word
Operand Instructions With Two- or Three-Operand
Reads On-Chip Peripherals
− Software-Programmable Wait-State
Generator and Programmable Bank
Switching
− On-Chip Phase-Locked Loop (PLL) Clock
Generator With Internal Oscillator or
External Clock Source
− Time-Division Multiplexed (TDM) Serial
Port
− Buffered Serial Port (BSP)
− 8-Bit Parallel Host Port Interface (HPI)
− One 16-Bit Timer
− External-Input/Output (XIO) Off Control
to Disable the External Data Bus,
Address Bus and Control Signals Power Consumption Control With IDLE1,
IDLE2, and IDLE3 Instructions With
Power-Down Modes CLKOUT Off Control to Disable CLKOUT On-Chip Scan-Based Emulation Logic,
IEEE Std 1149.1† (JTAG) Boundary Scan
Logic 12.5-ns Single-Cycle Fixed-Point
Instruction Execution Time (80 MIPS) for
3.3-V Power Supply) 10-ns Single-Cycle Fixed-Point Instruction
Execution Time (100 MIPS) for 3.3-V Power
Supply (2.5-V Core) 8.3-ns Single-Cycle Fixed-Point Instruction
Execution Time (120 MIPS) for 3.3-V Power
Supply (2.5-V Core) Available in a 144-Pin Plastic Thin Quad
Flatpack (TQFP) (PGE Suffix) and a 144-Pin
Ball Grid Array (BGA) (GGU Suffix) †IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
