TMS320UC5409GGUR80 ,Digital Signal Processor 144-BGA MICROSTAR -40 to 100Not Recommended For New Designs SPRS101E − APRIL 1999 − R ..
TMS320UC5409PGE-80 ,Digital Signal ProcessorNot Recommended For New Designs SPRS101E − APRIL 1999 − R ..
TMS320VC33PGE ,DIGITAL SIGNAL PROCESSORTMS320VC33DIGITALSIGNALPROCESSORSPRS087E -- FEBRUARY 1999 -- REVISED JANUARY 2004D High-Performance ..
TMS320VC33PGE120 ,Digital Signal ProcessorTMS320VC33DIGITALSIGNALPROCESSORSPRS087E -- FEBRUARY 1999 -- REVISED JANUARY 2004D High-Performance ..
TMS320VC33PGE150 ,Digital Signal ProcessorTMS320VC33DIGITALSIGNALPROCESSORSPRS087E -- FEBRUARY 1999 -- REVISED JANUARY 2004D High-Performance ..
TMS320VC33PGE-150 ,Digital Signal Processorfeatures.Please be aware that an important notice concerning availability, standard warranty, and u ..
TPS60151DRVR ,140mA, 5V Charge Pump in 2x2 QFN 6-WSON -40 to 85Features 3 DescriptionThe TPS60151 is a switched capacitor voltage1• 2.7 V to 5.5 V Input Voltage R ..
TPS601A ,PHOTOTRANSISTOR SILICON NPN EPITAXIAL PLANARTPS601ATP§601APHOTO TRANSISTOR FOR PHOTO SENSOR Unit in mmPHOTOELECTRIC COUNTERPOSITION DETECTIONVA ..
TPS60200DGS ,Regulated 3.3-V Low Ripple Charge Pump With Low Battery IndicatorFeatures 2 Applications1• Regulated 3.3-V Output Voltage With up to • Two Battery Cells to 3.3-V Co ..
TPS60201DGS ,Regulated 3.3-V Low Ripple Charge Pump With Power Good IndicatorFeatures 2 Applications1• Regulated 3.3-V Output Voltage With up to • Two Battery Cells to 3.3-V Co ..
TPS60203DGSR ,Regulated 3.3-V Low Ripple Charge Pump With Power Good IndicatorFeatures 2 Applications1• Regulated 3.3-V Output Voltage With up to • Two Battery Cells to 3.3-V Co ..
TPS60204DGS ,Regulated 3.3-V Low Ripple Charge Pump with Low Battery Indicatorfeatures10-pin MSOP With Only Four External Regulated 3.3-V Output Voltage With up toCapacitors Re ..
TMS320UC5409GGU-80-TMS320UC5409GGUR80-TMS320UC5409PGE-80
Digital Signal Processor
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SPRS101E − APRIL 1999 − REVISED OCTOBER 2008
Advanced Multibus Architecture With Three
Separate 16-Bit Data Memory Buses and
One Program Memory Bus 40-Bit Arithmetic Logic Unit (ALU),
Including a 40-Bit Barrel Shifter and Two
Independent 40-Bit Accumulators 17- × 17-Bit Parallel Multiplier Coupled to a
40-Bit Dedicated Adder for Non-Pipelined
Single-Cycle Multiply/Accumulate (MAC)
Operation Compare, Select, and Store Unit (CSSU) for
the Add/Compare Selection of the Viterbi
Operator Exponent Encoder to Compute an
Exponent Value of a 40-Bit Accumulator
Value in a Single Cycle Two Address Generators With Eight
Auxiliary Registers and Two Auxiliary
Register Arithmetic Units (ARAUs) Data Bus With a Bus-Holder Feature Extended Addressing Mode for 8M × 16-Bit
Maximum Addressable External Program
Space 16K x 16-Bit On-Chip ROM 32K x 16-Bit Dual-Access On-Chip RAM Single-Instruction-Repeat and
Block-Repeat Operations for Program Code Block-Memory-Move Instructions for Better
Program and Data Management Instructions With a 32-Bit Long Word
Operand Instructions With Two- or Three-Operand
Reads Arithmetic Instructions With Parallel Store
and Parallel Load Conditional Store Instructions Fast Return From Interrupt On-Chip Peripherals
− Software-Programmable Wait-State
Generator and Programmable Bank
Switching
− On-Chip Phase-Locked Loop (PLL) Clock
Generator With Internal Oscillator or
External Clock Source
− Three Multichannel Buffered Serial Ports
(McBSPs)
− Enhanced 8-Bit Parallel Host-Port
Interface With 16-Bit Data/Addressing
− One 16-Bit Timer
− Six-Channel Direct Memory Access
(DMA) Controller Power Consumption Control With IDLE1,
IDLE2, and IDLE3 Instructions With
Power-Down Modes CLKOUT Off Control to Disable CLKOUT On-Chip Scan-Based Emulation Logic,
IEEE Std 1149.1† (JTAG) Boundary Scan
Logic 12.5-ns Single-Cycle Fixed-Point
Instruction Execution Time (80 MIPS) 1.8-V Core Power Supply 1.8-V to 3.6-V I/O Power Supply Enables
Operation With a SIngle 1.8-V Supply or
With Dual Power Supplies Available in a 144-Pin Plastic Thin Quad
Flatpack (TQFP) (PGE Suffix) and a 144-Pin
Ball Grid Array (BGA) (GGU Suffix) All trademarks are the property of their respective owners.
†IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
