TMS320LC549GGU-80 ,Digital Signal Processor SPRS077B − SEPTEMBER 1998 − REVISED FEBRUARY 2000 Advanc ..
TMS320LC549PGE-66 ,Digital Signal ProcessorElectrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 13 Buffered Serial Port Tran ..
TMS320LC549PGE-80 ,Digital Signal ProcessorMaximum Ratings . . . . . . . . . . . . . . . . . . . . 11 Serial Port Receive Timing . . . . . . . ..
TMS320LF2401AVFA ,16-Bit Fixed-Point DSP with Flashblock diagram of the LC2401A device and development support DSP controller . . . . . . . . . . . . ..
TMS320LF2401AVFAR ,16-Bit Fixed-Point DSP with Flash 32-LQFP -40 to 85 SPRS161K − MARCH 2001 − REVISED JULY 2007 High-Performance ..
TMS320LF2401AVFS ,16-Bit Fixed-Point DSP with Flash 32-LQFP -40 to 125maximum ratings over memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 oper ..
TPS54672PWPR ,6-A Active Bus Termination/ DDR Memory DC/DC ConverterSLVS397C − JULY 2001 − REVISED FEBRUARY 2005
TPS54672PWPR G4 ,6-A Active Bus Termination/ DDR Memory DC/DC Converter SLVS397C − JULY 2001 − REVISED FEBRUARY 2005 ..
TPS54672PWPRG4 ,6-A Active Bus Termination/ DDR Memory DC/DC Converter SLVS397C − JULY 2001 − REVISED FEBRUARY 2005
TPS54673 ,Low Input Voltage 6A Continuous Buck Converter with Disabled Sinking During Start UpELECTRICAL CHARACTERISTICS TJ = −40°C to 125°C, V = 3 V to 6 V (unless otherwise noted)IPARAMETER ..
TPS54673PWPR ,Low Input Voltage 6A Synchronous Buck Converter with Disabled Sinking During Start Upfeatures are a true, high performance,voltage error amplifier that enables maximum Wide PWM Freque ..
TPS54673PWPRG4 ,Low Input Voltage 6A Synchronous Buck Converter with Disabled Sinking During Start Upmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
TMS320LC549GGU-80-TMS320LC549PGE-66-TMS320LC549PGE-80
Digital Signal Processor
Independent 40-Bit Accumulators 17- × 17-Bit Parallel Multiplier Coupled to a
40-Bit Dedicated Adder for Non-Pipelined
Single-Cycle Multiply/Accumulate (MAC)
Operation Compare, Select, and Store Unit (CSSU) for
the Add/Compare Selection of the Viterbi
Operator Exponent Encoder to Compute an
Exponent Value of a 40-Bit Accumulator
Value in a Single Cycle Two Address Generators With Eight
Auxiliary Registers and Two Auxiliary
Register Arithmetic Units (ARAUs) Data Bus With a Bus Holder Feature Address Bus With a Bus Holder Feature Extended Addressing Mode for 8M × 16-Bit
Maximum Addressable External Program
Space 192K × 16-Bit Maximum Addressable
Memory Space (64K Words Program,
64K Words Data, and 64K Words I/O) On-Chip ROM with Some Configurable to
Program/Data Memory Dual-Access On-Chip RAM Single-Access On-Chip RAM Single-Instruction Repeat and
Block-Repeat Operations for Program Code Block-Memory-Move Instructions for Better
Program and Data Management
and Parallel Load Conditional Store Instructions Fast Return From Interrupt On-Chip Peripherals
− Software-Programmable Wait-State
Generator and Programmable Bank
Switching
− On-Chip Phase-Locked Loop (PLL) Clock
Generator With Internal Oscillator or
External Clock Source
− Time-Division Multiplexed (TDM) Serial
Port
− Buffered Serial Port (BSP)
− 8-Bit Parallel Host-Port Interface (HPI)
− One 16-Bit Timer
− External-Input/Output (XIO) Off Control
to Disable the External Data Bus,
Address Bus and Control Signals Power Consumption Control With IDLE1,
IDLE2, and IDLE3 Instructions With
Power-Down Modes CLKOUT Off Control to Disable CLKOUT On-Chip Scan-Based Emulation Logic,
IEEE Std 1149.1† (JTAG) Boundary Scan
Logic 15-ns Single-Cycle Fixed-Point Instruction
Execution Time (66 MIPS) for 3.3-V Power
Supply 12.5-ns Single-Cycle Fixed-Point
Instruction Execution Time (80 MIPS) for
3.3-V Power Supply †IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
