TMS320LC548GGU-66 ,Digital Signal Processor 144-BGA MICROSTAR TMS320LC548FIXED-POINTDIGITALSIGNALPROCESSORSPRS123 -- FEBRUARY 2000D AdvancedMultibusArchitectureW ..
TMS320LC548GGU-80 ,Digital Signal Processor 144-BGA MICROSTAR Maximum Ratings.. 11 Serial Port Receive Timing .. 41Recommended Operating Conditions .. 11 Serial ..
TMS320LC548PGE-66 ,Digital Signal Processor 144-LQFP TMS320LC548FIXED-POINTDIGITALSIGNALPROCESSORSPRS123 -- FEBRUARY 2000D AdvancedMultibusArchitectureW ..
TMS320LC548PGE80 ,Digital Signal Processor 144-LQFP Maximum Ratings.. 11 Serial Port Receive Timing .. 41Recommended Operating Conditions .. 11 Serial ..
TMS320LC548PGE-80 ,Digital Signal Processor 144-LQFP TMS320LC548FIXED-POINTDIGITALSIGNALPROCESSORSPRS123 -- FEBRUARY 2000D AdvancedMultibusArchitectureW ..
TMS320LC549GGU , FIXED-POINT DIGITAL SIGNAL PROCESSOR
TPS54622RHLR ,4.5-V to 17-V Input, 6-A Synchronous Step Down SWIFT? Converter With Hiccup Protection 14-VQFN -40 to 150Block Diagram... 1211.7 Glossary. 367.3 Feature Description.... 1212 Mechanical, Packaging, and Ord ..
TPS54623RHLR ,4.5V to 17V Input, 6A Synchronous Step-Down SWIFT Converter with Light Load Efficiency 14-VQFN -40 to 150Features 3 DescriptionThe TPS54623 in thermally enhanced VQFN1• Integrated 26 mΩ, 19 mΩ MOSFETspack ..
TPS54628DDAR ,4.5V to 18V Input, 6-A Synchronous Step-Down Converter with Eco-mode? 8-SO PowerPAD -40 to 125Features 3 DescriptionThe TPS54628 device is an adaptive on-time D-1• D-CAP2™ Mode Enables Fast Tra ..
TPS54672 ,6-A Active Bus Termination Switcher with Integrated FETsSLVS397C − JULY 2001 − REVISED FEBRUARY 2005These devices have limited built-in ESD protection. The ..
TPS54672PWP ,6-A Active Bus Termination/ DDR Memory DC/DC ConverterMAXIMUM RATINGS(1)over operating free-air temperature range unless otherwise notedTPS54672VIN, ENA ..
TPS54672PWPG4 ,6-A Active Bus Termination/ DDR Memory SWIFT? Converter 28-HTSSOP -40 to 85FEATURES DESCRIPTION Tracks Externally Applied Reference VoltageAs a member of the SWIFT family o ..
TMS320LC548GGU-66-TMS320LC548GGU-80-TMS320LC548PGE-66-TMS320LC548PGE80-TMS320LC548PGE-80
FIXED-POINT DIGITAL SIGNAL PROCESSORS
TMS320LC548FIXED-POINT DIGITAL SIGNAL PROCESSORSPRS123-- FEBRUARY 2000
Advanced Multibus Architecture With ThreeSeparate 16-Bit Data Memory Buses andOne Program Memory Bus 40-Bit Arithmetic Logic Unit (ALU)Includinga 40-Bit Barrel Shifter and TwoIndependent 40-Bit Accumulators 17-
17-Bit Parallel Multiplier Coupledtoa40-Bit Dedicated Adder for Non-PipelinedSingle-Cycle Multiply/Accumulate (MAC)Operation Compare, Select, and Store Unit (CSSU) forthe Add/Compare Selectionof the ViterbiOperator Exponent Encoderto ComputeanExponent Valueofa 40-Bit AccumulatorValueinaSingleCycle Two Address Generators With EightAuxiliary Registers and Two AuxiliaryRegister Arithmetic Units (ARAUs) Data Bus Witha Bus Holder Feature Address Bus Witha Bus Holder Feature Extended Addressing Mode for 8M
16-BitMaximum Addressable External ProgramSpace 192K
16-Bit Maximum AddressableMemory Space (64K Words Program,64K Words Data, and 64K Words I/O) On-Chip ROM with Some ConfigurabletoProgram/Data Memory Dual-Access On-Chip RAM Single-Access On-Chip RAM Single-Instruction Repeat andBlock-Repeat Operations for Program Code Block-Memory-Move Instructions for BetterProgram and Data Management Instructions Witha 32-Bit Long WordOperand Instructions With Two-or Three-OperandReads Arithmetic Instructions With Parallel Storeand Parallel Load Conditional Store Instructions Fast Return From Interrupt On-Chip Peripherals-- Software-Programmable Wait-StateGenerator and Programmable BankSwitching-- On-Chip Phase-Locked Loop (PLL) ClockGenerator With Internal OscillatororExternal Clock Source-- Time-Division Multiplexed (TDM) SerialPort-- Buffered Serial Port (BSP)-- 8-Bit Parallel Host Port Interface (HPI)-- One 16-Bit Timer-- External-Input/Output (XIO) Off Controlto Disable the External Data Bus,Address Bus and Control Signals Power Consumption Control With IDLE1,IDLE2, and IDLE3 Instructions WithPower-Down Modes CLKOUT Off Controlto Disable CLKOUT On-Chip Scan-Based Emulation Logic,IEEE Std 1149.1† (JTAG) Boundary ScanLogic 15-ns Single-Cycle Fixed-Point InstructionExecution Time (66 MIPS) for 3.3-V PowerSupply 12.5-ns Single-Cycle Fixed-PointInstruction Execution Time (80 MIPS) for3.3-V Power SupplyPleasebe aware thatan important notice concerning availability, standard warranty, and usein critical applicationsof
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