TMS320LC542PGE2-40 ,Digital Signal Processorfeatures of eachdevice including the capacity of on-chip RAM and ROM memories, the peripherals, the ..
TMS320LC543 ,Digital Signal Processor TMS320C54x, TMS320LC54x, TMS320VC54xFIXED-POINT DIGITAL SIGNAL PROCESSORSSPRS039C – FEBRUARY 1996 ..
TMS320LC543PZ1-40 ,Digital Signal Processorfeatures of eachdevice including the capacity of on-chip RAM and ROM memories, the peripherals, the ..
TMS320LC543PZ2-40 ,Digital Signal Processorfeatures of eachdevice including the capacity of on-chip RAM and ROM memories, the peripherals, the ..
TMS320LC545A ,Digital Signal Processor
TMS320LC546A ,Digital Signal Processor
TPS54620RGYR ,4.5V to 17V Input, 6A Synchronous Step-Down SWIFT? Converter 14-VQFN -40 to 150Maximum Ratings table 5• Changed Handling Ratings table to ESD Ratings...... 5• Changed RHY package ..
TPS54620RGYT ,4.5V to 17V Input, 6A Synchronous Step-Down SWIFT? Converter 14-VQFN -40 to 150Features 3 DescriptionThe TPS54620 in thermally enhanced 3.50 mm ×1• Integrated 26 mΩ and 19 mΩ MOS ..
TPS54620RHLR ,4.5V to 17V Input, 6A Synchronous Step-Down SWIFT? Converter 14-VQFN -40 to 150/swiftprevents current runaway. There is also a low-side• Create a Custom Design Using the TPS54620 ..
TPS54620RHLT ,4.5V to 17V Input, 6A Synchronous Step-Down SWIFT? Converter 14-VQFN -40 to 150Block Diagram... 1211.6 Glossary. 377.3 Feature Description.... 1212 Mechanical, Packaging, and Ord ..
TPS54622RHLR ,4.5-V to 17-V Input, 6-A Synchronous Step Down SWIFT? Converter With Hiccup Protection 14-VQFN -40 to 150Block Diagram... 1211.7 Glossary. 367.3 Feature Description.... 1212 Mechanical, Packaging, and Ord ..
TPS54623RHLR ,4.5V to 17V Input, 6A Synchronous Step-Down SWIFT Converter with Light Load Efficiency 14-VQFN -40 to 150Features 3 DescriptionThe TPS54623 in thermally enhanced VQFN1• Integrated 26 mΩ, 19 mΩ MOSFETspack ..
TMS320LC542-TMS320LC542PGE1-40-TMS320LC542PGE2-40
Digital Signal Processor
Independent 40-Bit Accumulators 17- × 17-Bit Parallel Multiplier Coupled to a
40-Bit Dedicated Adder for Non-Pipelined
Single-Cycle Multiply/Accumulate (MAC)
Operation Compare, Select, and Store Unit (CSSU) for
the Add/Compare Selection of the Viterbi
Operator Exponent Encoder to Compute an
Exponent Value of a 40-Bit Accumulator
Value in a Single Cycle Two Address Generators With Eight
Auxiliary Registers and Two Auxiliary
Register Arithmetic Units (ARAUs) Data Bus With a Bus Holder Feature Address Bus With a Bus Holder Feature
(’548 and ’549 Only) Extended Addressing Mode for 8M × 16-Bit
Maximum Addressable External Program
Space (’548 and ’549 Only) 192K × 16-Bit Maximum Addressable
Memory Space (64K Words Program,
64K Words Data, and 64K Words I/O) On-Chip ROM with Some Configurable to
Program/Data Memory Dual-Access On-Chip RAM Single-Access On-Chip RAM (’548/’549) Single-Instruction Repeat and
Block-Repeat Operations for Program Code Block-Memory-Move Instructions for Better
Program and Data Management Instructions With a 32-Bit Long Word
Operand Instructions With Two- or Three-Operand
Reads Arithmetic Instructions With Parallel Store
and Parallel Load Conditional Store Instructions
– On-Chip Phase-Locked Loop (PLL) Clock
Generator With Internal Oscillator or
External Clock Source
– Full-Duplex Serial Port to Support 8- or
16-Bit Transfers (’541, ’LC545, and
’LC546 Only)
– Time-Division Multiplexed (TDM) Serial
Port (’542, ’543, ’548, and ’549 Only)
– Buffered Serial Port (BSP) (’542, ’543,
’LC545, ’LC546, ’548, and ’549 Only)
– 8-Bit Parallel Host-Port Interface (HPI)
(’542, ’LC545, ’548, and ’549)
– One 16-Bit Timer
– External-Input/Output (XIO) Off Control
to Disable the External Data Bus,
Address Bus and Control Signals Power Consumption Control With IDLE1,
IDLE2, and IDLE3 Instructions With
Power-Down Modes CLKOUT Off Control to Disable CLKOUT On-Chip Scan-Based Emulation Logic,
IEEE Std 1149.1† (JTAG) Boundary Scan
Logic 25-ns Single-Cycle Fixed-Point Instruction
Execution Time [40 MIPS] for 5-V Power
Supply (’C541 and ’C542 Only) 20-ns and 25-ns Single-Cycle Fixed-Point
Instruction Execution Time (50 MIPS and
40 MIPS) for 3.3-V Power Supply (’LC54x) 15-ns Single-Cycle Fixed-Point Instruction
Execution Time (66 MIPS) for 3.3-V Power
Supply (’LC54xA, ’548, ’LC549) 12.5-ns Single-Cycle Fixed-Point
Instruction Execution Time (80 MIPS) for
3.3-V Power Supply (’LC548, ’LC549) 10-ns and 8.3-ns Single-Cycle Fixed-Point
Instruction Execution Time (100 and 120
MIPS) for 3.3-V Power Supply (2.5-V Core)
(’VC549) Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
†IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
