TMS320LBC53SPZ-80 ,Digital Signal Processor 100-LQFP
TMS320LC203PZA ,Digital Signal Processor 'NRND' (Not Recommended for New Designs)
TMS320LC50PQ57 ,Digital Signal Processors 132-BQFP
TMS320LC541BPZ-66 ,Digital Signal Processor TMS320C54x, TMS320LC54x, TMS320VC54xFIXED-POINT DIGITAL SIGNAL PROCESSORSSPRS039C – FEBRUARY 1996 ..
TMS320LC542 ,Digital Signal Processor TMS320C54x, TMS320LC54x, TMS320VC54xFIXED-POINT DIGITAL SIGNAL PROCESSORSSPRS039C – FEBRUARY 1996 ..
TMS320LC542 ,Digital Signal Processor TMS320C54x, TMS320LC54x, TMS320VC54xFIXED-POINT DIGITAL SIGNAL PROCESSORSSPRS039C – FEBRUARY 1996 ..
TPS54616 ,Low Input Voltage 6A Continuous Buck Converter with 3.3V Output SLVS400D–AUGUST 2001–REVISED JANUARY 20155 Pin Configuration and FunctionsTPS5461x PWP Package28-P ..
TPS54616PWP ,Low Input Voltage 6A Synchronous Buck Converter with 3.3V OutputMaximum Ratings(1)over operating free-air temperature range (unless otherwise noted)MIN MAX UNITVIN ..
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TPS54616QPWPRQ1 ,Low Input Voltage 6A Synchronous Buck Converter with 3.3V OutputFEATURES DESCRIPTION Qualified for Automotive ApplicationsThe SWIFT family of dc/dc regulators, t ..
TMS320LBC53SPZ-80
Digital Signal Processor 100-LQFP
Execution Time for 3-V Operation Single-Cycle 16 × 16-Bit Multiply/Add 224K × 16-Bit Maximum Addressable
External Memory Space (64K Program, 64K
Data, 64K I/O, and 32K Global) 2K, 4K, 8K, 16K, 32K × 16-Bit Single-Access
On-Chip Program ROM 1K, 3K, 6K, 9K × 16-Bit Single-Access
On-Chip Program/Data RAM (SARAM) 1K Dual-Access On-Chip Program/Data
RAM (DARAM) Full-Duplex Synchronous Serial Port for
Coder/Decoder Interface Time-Division-Multiplexed (TDM) Serial Port Hardware or Software Wait-State
Generation Capability On-Chip Timer for Control Operations Repeat Instructions for Efficient Use of
Program Space Buffered Serial Port Host Port Interface On-Chip Scan-Based Emulation Logic Boundary Scan Five Packaging Options
– 100-Pin Quad Flat Package (PJ Suffix)
– 100-Pin Thin Quad Flat Package
(PZ Suffix)
– 128-Pin Thin Quad Flat Package
(PBK Suffix)
– 132-Pin Quad Flat Package (PQ Suffix)
– 144-Pin Thin Quad Flat Package
(PGE Suffix) Low Power Dissipation and Power-Down
Modes:
– 47 mA (2.35 mA/MIP) at 5 V, 40-MHz
Clock (Average)
– 23 mA (1.15 mA/MIP) at 3 V, 40-MHz
Clock (Average)
– 10 mA at 5 V, 40-MHz Clock (IDLE1 Mode)
– 3 mA at 5 V, 40-MHz Clock (IDLE2 Mode)
– 5 m A at 5 V, Clocks Off (IDLE2 Mode) High-Performance Static CMOS Technology IEEE Standard 1149.1† Test-Access Port
(JTAG)
descriptionThe TMS320C5x generation of the Texas Instruments (TI) TMS320 digital signal processors (DSPs) is
fabricated with static CMOS integrated circuit technology; the architectural design is based upon that of an
earlier TI DSP, the TMS320C25. The combination of advanced Harvard architecture, on-chip peripherals,
on-chip memory, and a highly specialized instruction set is the basis of the operational flexibility and speed of
the ’C5x‡ devices. They execute up to 50 million instructions per second (MIPS).
The ’C5x devices offer these advantages: Enhanced TMS320 architectural design for increased performance and versatility- Modular architectural design for fast development of spin-off devices- Advanced integrated-circuit processing technology for increased performance- Upward-compatible source code (source code for ’C1x and ’C2x DSPs is upward compatible with ’C5x DSPs.)- Enhanced TMS320 instruction set for faster algorithms and for optimized high-level language operation- New static-design techniques for minimizing power consumption and maximizing radiation tolerance
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TI is a trademark of . †IEEE Standard 1149.1–1990, IEEE Standard Test-Access Port and Boundary-Scan Architecture
‡References to ’C5x in this document include both TMS320C5x and TMS320LC5x devices unless specified otherwise.
