TMS320DM643AGDK5 ,Video/Imaging Fixed-Point Digital Signal ProcessoThe TMS320C64x™ DSPs (including the TMS320DM643 device) are the highest-performance fixed-pointDSP ..
TMS320DM643AZDK6 ,Video/Imaging Fixed-Point Digital Signal Processo SPRS269D–FEBRUARY 2005–REVISED OCTOBER 2010The VCXO interpolated control (VIC) port provides digit ..
TMS320DM643AZNZ6 ,Video/Imaging Fixed-Point Digital Signal Processor 548-FCBGA The TMS320C64x™ DSPs (including the TMS320DM643 device) are the highest-performance fixed-pointDSP ..
TMS320DM6441AZWT ,DaVinci Digital Media System-on-Chip 361-NFBGA • Video Processing Subsystem (Continued) • One Serial Port Interface (SPI) With TwoChip-Selects– Ba ..
TMS320DM6441ZWT ,DaVinci Digital Media System-on-Chip 361-NFBGA Features12• High-Performance Digital Media SoC • C64x+ L1/L2 Memory Architecture– C64x+™ DSP Clock ..
TMS320DM6443AZWT ,DaVinci Digital Media System-on-Chip 361-NFBGA Features12• High-Performance Digital Media SoC • C64x+ L1/L2 Memory Architecture– 594-MHz C64x+™ Cl ..
TPS54310 ,Low Input Voltage 3A Buck Converter with Adjustable Output VoltageSample & Support &Product Tools &TechnicalCommunityBuyFolder Documents SoftwareTPS54310SLVS412E–DEC ..
TPS54310PWP ,Q1Table of Contents8.2 Functional
TPS54310PWPG4 ,Q1Maximum Ratings.. 411.1 Layout Guidelines.... 187.2 ESD Ratings........ 411.2 Layout Example....... ..
TPS54310PWPR ,Q1Features... 18.3 Feature Description.... 102 Applications..... 18.4 Device Functional Modes.... 123 ..
TPS54310PWPRG4 ,3V to 6V Input, 3A Synchronous Step-Down SWIFT? Converter 20-HTSSOP -40 to 125features are a true,• Externally Compensated for Design Flexibility high performance, voltage error ..
TPS54310QPWPRQ1 ,Q1 TPS54310-Q1SGLS280D − JANUARY 2005 − REVISED JUNE 2009RECOMMENDED OPERATING CONDITIONSMIN NOM MAX ..
TMS320DM643AGDK5
Video/Imaging Fixed-Point Digital Signal Processo
TMS320DM643
www.ti.com SPRS269D–FEBRUARY 2005–REVISED OCTOBER 2010
TMS320DM643
Video/Imaging Fixed-Point Digital Signal Processor
Checkfor Samples: TMS320DM643 TMS320DM643 Video/Imaging Fixed-Point Digital Signal Processor
Synchronous Memories (SDRAM, SBSRAM,• High-Performance Digital Media Processor ZBT SRAM, and FIFO)– 2-, 1.67-ns Instruction Cycle Time – 1024M-Byte Total Addressable External– 500-, 600-MHz Clock Rate Memory Space– Eight 32-Bit Instructions/Cycle • Enhanced Direct-Memory-Access (EDMA)– 4000, 4800 MIPS Controller (64 Independent Channels)– Fully Software-Compatible With C64x™ • 10/100 Mb/s Ethernet MAC (EMAC)• VelociTI.2™ Extensionsto VelociTI™ – IEEE 802.3 CompliantAdvanced Very-Long-Instruction-Word (VLIW) – Media Independent Interface (MII)TMS320C64x™ DSP Core –8 Independent Transmit (TX) Channels and1– Eight Highly Independent Functional Units Receive (RX) ChannelWith VelociTI.2™ Extensions: • Management Data Input/Output (MDIO)• Six ALUs (32-/40-Bit), Each Supports Two Configurable Video Ports (VP1, VP2)Single 32-Bit, Dual 16-Bit,or Quad 8-Bit
Arithmetic per Clock Cycle – Providinga GluelessI/Fto Common Video
Decoder and Encoder Devices• Two Multipliers Support Four16x 16-Bit
Multiplies (32-Bit Results) per Clock – Supports Multiple Resolutions/Video Stds
Cycleor Eight8x 8-Bit Multiplies (16-Bit • VCXO Interpolated Control Port (VIC)Results) per Clock Cycle – Supports Audio/Video Synchronization– Load-Store Architecture With Non-Aligned • Host-Port Interface (HPI) [32-/16-Bit]Support • Multichannel Audio Serial Port (McASP)– 64 32-Bit General-Purpose Registers – Eight Serial Data Pins– Instruction Packing Reduces Code Size – Wide VarietyofI2S and Similar Bit Stream– All Instructions Conditional Format• Instruction Set Features – Integrated Digital AudioI/F Transmitter– Byte-Addressable (8-/16-/32-/64-Bit Data) Supports S/PDIF, IEC60958-1, AES-3, CP-430 8-Bit Overflow Protection Formats Bit-Field Extract, Set, Clear • Inter-Integrated Circuit(I2C Bus™) Bit-Counting • Multichannel Buffered Serial Port – CLKS Input Not Supported • Three 32-Bit General-Purpose Timers L1P Program Cache • Sixteen General-Purpose I/O (GPIO) Pins Generator Data • IEEE-1149.1 (JTAG) Boundary- Scan-Compatible Mapped • 548-Pin Ball Grid Array (BGA) PackageRAM/Cache (GDK and ZDK Suffixes), Pitch • 548-Pin Ball Grid Array (BGA) Package (GNZ and ZNZ Suffixes), 1.0-mm (EMIF) • 0.13-µ m/6-Level • 3.3-V and • 3.3-V I/O, 1.4-V Internal (-600)
