TMS320DM642AGNZ6 ,Video/Imaging Fixed-Point Digital Signal Processor 548-FCBGA TMS320DM642
TMS320DM642AZDK5 ,Video/Imaging Fixed-Point Digital Signal Processor 548-FCBGA SPRS200N–JULY 2002–REVISED OCTOBER 2010TMS320DM642Video/Imaging Fixed-Point Digital Signal Process ..
TMS320DM642AZDK6 ,Video/Imaging Fixed-Point Digital Signal Processor 548-FCBGA FeaturesFormats– Byte-Addressable (8-/16-/32-/64-Bit Data)– Integrated Digital Audio I/F Transmitte ..
TMS320DM642AZDK7 ,Video/Imaging Fixed-Point Digital Signal Processor 548-FCBGA The TMS320C64x™ DSPs (including the TMS320DM642 device) are the highest-performance fixed-pointDSP ..
TMS320DM642AZDKA6 ,Video/Imaging Fixed-Point Digital Signal Processor 548-FCBGA Block DiagramFigure 1-1 shows the functional
TMS320DM642AZNZ5 ,Video/Imaging Fixed-Point Digital Signal Processor 548-FCBGA features, such as the bad clock detectioncircuit for each high-frequency master clock which verifie ..
TPS54260DGQ ,3.5V to 60V Input, 2.5A Step-Down Converter with Eco-Mode 10-MSOP-PowerPAD -40 to 125 SLVSA86C–MARCH 2010–REVISED MAY 20165 Pin Configuration and FunctionsDGQ PackageDRC Package10-Pin ..
TPS54260DGQR ,3.5V to 60V Input, 2.5A Step-Down Converter with Eco-Mode 10-MSOP-PowerPAD -40 to 125Features 3 DescriptionThe TPS54260 device is a 60-V, 2.5-A, step down1• 3.5-V to 60-V Input Voltage ..
TPS54283PWP ,4.5V to 28V Input, Dual 2A Output, 300kHz Step-Down Converter with Internal Compensation 14-HTSSOP -40 to 85Maximum Ratings are exceeded. Functional operation should be limited to theRecommended DC Operating ..
TPS54283PWPR ,4.5V to 28V Input, Dual 2A Output, 300kHz Step-Down Converter with Internal Compensation 14-HTSSOP -40 to 85features with a minimum ofexternal components. Channel 1 overcurrent• Current Mode Controlprotectio ..
TPS54283PWPRG4 ,4.5V to 28V Input, Dual 2A Output, 300kHz Step-Down Converter with Internal Compensation 14-HTSSOP -40 to 85SLUS749C–JULY 2007–REVISED OCTOBER 2007These devices have limited built-in ESD protection. The lead ..
TPS54286PWP ,4.5V to 28V Input, Dual 2A Output, 600kHz Step-Down Converter with Internal Compensation 14-HTSSOP -40 to 85features with a minimum ofexternal components. Channel 1 overcurrent• Current Mode Controlprotectio ..
TMS320DM642AGDK6-TMS320DM642AGDKA5-TMS320DM642AGNZ6-TMS320DM642AZDK5-TMS320DM642AZDK6-TMS320DM642AZDK7-TMS320DM642AZDKA6-TMS320DM642AZNZ5-TMS320DM642AZNZ6-TMS320DM642AZNZ7-TMS320DM642AZNZA6-TMS320DM642GDK 720-TMS320DM642GDK600-TMS320DM642GNZ500-TMS320DM642GNZA500
Video/Imaging Fixed-Point Digital Signal Processor
TMS320DM642
www.ti.com SPRS200N–JULY 2002–REVISED OCTOBER 2010
TMS320DM642
Video/Imaging Fixed-Point Digital Signal Processor
Checkfor Samples: TMS320DM642 TMS320DM642 Video/Imaging Fixed-Point Digital Signal Processor
123 1024M-Byte Total Addressable External• High-Performance Digital Media Processor Memory Space– 2-, 1.67-, 1.39-ns Instruction Cycle Time • Enhanced Direct-Memory-Access (EDMA)– 500-, 600-, 720-MHz Clock Rate Controller (64 Independent Channels)– Eight 32-Bit Instructions/Cycle • 10/100 Mb/s Ethernet MAC (EMAC)– 4000, 4800, 5760 MIPS – IEEE 802.3 Compliant– Fully Software-Compatible With C64x™ – Media Independent Interface (MII)• VelociTI.2™ Extensionsto VelociTI™ –8 Independent Transmit (TX) Channels and1Advanced Very-Long-Instruction-Word (VLIW) Receive (RX) ChannelTMS320C64x™ DSP Core • Management Data Input/Output (MDIO)– Eight Highly Independent Functional Units • Three Configurable Video PortsWith VelociTI.2™ Extensions: Providinga GluelessI/Fto Common Video• Six ALUs (32-/40-Bit), Each Supports
Decoder and Encoder DevicesSingle 32-Bit, Dual 16-Bit,or Quad 8-Bit
Arithmetic per Clock Cycle – Supports Multiple Resolutions/Video Stds Two Multipliers Support Four16x 16-Bit • VCXO Interpolated Control Port (VIC)
Multiplies (32-Bit Results) per Clock – Supports Audio/Video SynchronizationCycleor Eight8x 8-Bit Multiplies (16-Bit • Host-Port Interface (HPI) [32-/16-Bit]Results) per Clock Cycle • 32-Bit/66-MHz, 3.3-V Peripheral Component– Load-Store Architecture With Non-Aligned Interconnect (PCI) Master/Slave InterfaceSupport Conformsto PCI Specification 2.2– 64 32-Bit General-Purpose Registers • Multichannel Audio Serial Port (McASP) Instruction Packing Reduces Code Size – Eight Serial Data Pins– All Instructions Conditional – Wide VarietyofI2S and Similar Bit Stream• Instruction Set Features Formats Byte-Addressable (8-/16-/32-/64-Bit Data) – Integrated Digital AudioI/F Transmitter 8-Bit Overflow Protection Supports S/PDIF, IEC60958-1, AES-3, CP-430
Formats– Bit-Field Extract, Set, Clear Inter-Integrated Circuit(I2C Bus™) Bit-Counting Two Multichannel Buffered Serial Ports Three 32-Bit General-Purpose Timers Sixteen General-Purpose I/O (GPIO) Pins L1P Program Cache Generator Data • IEEE-1149.1 (JTAG) Boundary-Scan-Compatible • 548-Pin Ball Grid Package Mapped (GDK and ZDK Suffixes), 0.8-mm
RAM/Cache Allocation) • 548-Pin Ball Grid Array (BGA) Package (GNZ and ZNZ Suffixes), 1.0-mm Pitch (EMIF) • 0.13-µ m/6-Level Cu Process • 3.3-V I/O, 1.2-V and • 3.3-V -600, SBSRAM, -720)
