TMS320DM357ZWT ,Digital Media System-on-Chip (DMSoC) 361-NFBGA • IEEE-1149.1 (JTAG) Boundary- • 0.09-μm/6-Level Cu Metal Process (CMOS)Scan-Compatible• 3.3-V and ..
TMS320DM365 ,DaVinci Digital Media Processor• Hardware 3A statistics collection module• Four 64-Bit General-Purpose Timers (each(H3A) configura ..
TMS320DM365ZCE27 ,DaVinci Digital Media Processor 338-NFBGA 0 to 85features a suite of peripheralssaving developers on system costs.This ARM9-based DM365 device offer ..
TMS320DM365ZCE30 ,DaVinci Digital Media Processor 338-NFBGA 0 to 85Features12– Support for 32-Bit and 16-Bit• Highlights(Thumb® Mode) Instruction Sets– High-Performan ..
TMS320DM365ZCED30 ,DaVinci Digital Media Processor 338-NFBGA -40 to 85 SPRS457E–MARCH 2009–REVISED JUNE 20111.2 DescriptionDevelopers can now deliver pixel-perfect image ..
TMS320DM365ZCEF ,DaVinci Digital Media Processor 338-NFBGA 0 to 85block diagram of the TMS320DM365 device.16 Bit16-BitDDR2Camera IPIPEEDMA DDR2/ISIFControllerAFEmDDR ..
TPS54218RTER ,2.95V to 6V Input, 2A Synchronous Step-Down SWIFT? Converter 16-WQFN -40 to 150Features 3 DescriptionTheTPS54218 device is a full-featured, 6-V, 2-A,1• Two, 30-mΩ (typical) MOSFE ..
TPS54225 ,4.5V to 18V Input, 2A Synchronous Step-Down Converter 14-HTSSOP -40 to 85maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functio ..
TPS54225 ,4.5V to 18V Input, 2A Synchronous Step-Down Converter 14-HTSSOP -40 to 85ELECTRICAL CHARACTERISTICSover operating free-air temperature range, V , V = 12V (unless otherwise ..
TPS54225PWP ,4.5V to 18V Input, 2A Synchronous Step-Down Converter 14-HTSSOP -40 to 85FEATURESDESCRIPTION23• D-CAP2™ Mode Enables Fast TransientResponseThe TPS54225 is an adaptive on-ti ..
TPS54225PWPR ,4.5V to 18V Input, 2A Synchronous Step-Down Converter 14-HTSSOP -40 to 85features an adjustable slow start time and apower good function. The TPS54225 is available in• Powe ..
TPS54226 FEATURES APPLICATIONS23• D-CAP2™ Mode Enables Fast Transient• Wide Range of Applications for Low Vo ..
TMS320DM357ZWT
Digital Media System-on-Chip (DMSoC) 361-NFBGA
Digital Media System-on-Chip (DMSoC)1.1 Features
TMS320DM357
Digital Media System-on-Chipwww.ti.com SPRS553–NOVEMBER 2008
Digital Output•
High-Performance Digital Media SoC 8-/16-bit YUVor upto 24-Bit RGB– 270-MHz ARM926EJ-S™ Core Upto2 Video Windows– Fully Software-Compatible With ARM9™ External Memory Interfaces (EMIFs)•
ARM926EJ-S Core 32-Bit DDR2 SDRAM Memory Controller– Support for 32-Bit and 16-Bit (Thumb®
With 256M-Byte Address Space (1.8-V I/O)Mode) Instruction Sets Asynchronous 16-Bit Wide EMIF (EMIFA)– ARM® Jazelle® Technology
With 128M-Byte Address Reach– EmbeddedICE-RT™ Logic for Real-Time Flash Memory InterfacesDebug NOR (8-/16-Bit-Wide Data)•
ARM9 Memory Architecture NAND (8-/16-Bit-Wide Data)– 16K-Byte Instruction Cache Flash Card Interfaces– 8K-Byte Data Cache Multimedia Card (MMC)/Secure Digital (SD)– 16K-Byte RAM
with Secure Data I/O (SDIO)– 8K-Byte ROM SmartMedia•
H.264/MPEG4/JPEG Coprocessor Enhanced Direct-Memory-Access (EDMA)– Fixed Function Coprocessor Supports:
Controller (64 Independent Channels)•
H.264 BP Codecat D1, VGA, SIF Two 64-Bit General-Purpose Timers (Each•
MPEG4 SP Codecat D1, VGA, SIF
Configurableas Two 32-Bit Timers)•
JPEG Codec One 64-Bit Watch Dog Timer•
Embedded Trace Buffer™ (ETB11™) With 4KB
Memory for ARM9 Debug •
Three UARTs (One with RTS and CTS Flow
Control)•
Endianness: Little Endian One Serial Peripheral Interface (SPI) With Two•
Video Processing Subsystem Chip-Selects– Front End Provides: Master/Slave Inter-Integrated Circuit(I2C•
CCD and CMOS Imager Interface
Bus™)•
BT.601/BT.656 Digital YCbCr 4:2:2
(8-/16-Bit) Interface •
Audio Serial Port (ASP) Preview Engine for Real-Time Image – I2S
Processing – AC97 Audio Codec Interface•
Glueless Interfaceto Common Video – Standard Voice Codec Interface (AIC12)Decoders •
10/100 Mb/s Ethernet Media Access Controller•
Histogram Module (EMAC)•
Auto-Exposure, Auto-White Balance and – IEEE 802.3 CompliantAuto-Focus Module – Media Independent Interface (MII)•
Resize Engine •
Host Port Interface (HPI) with 16-Bit– Resize Images From 1/4xto4x Multiplexed Address/Data– Separate Horizontal/Vertical Control •
USB2.0 OTG Controller With Integrated– Back End Provides: High-Speed 2.0 PHY•
Hardware On-Screen Display (OSD) Three Pulse Width Modulator (PWM) Outputs•
3- 54-MHz DACs fora Combination of: On-Chip ARM ROM Bootloader (RBL)to Boot– Composite NTSC/PAL Video
From NAND Flashor UART– Luma/Chroma Separate Video
(S-video) •
Comprehensive Power-Saving Modes Component (YPbPror RGB) Video •
Flexible PLL Clock Generators(Progressive/Interlaced)
