TMS320C6745BPTP3 ,Fixed/Floating-Point Digital Signal Processor 176-HLQFP 0 to 90• PRUSS can be Disabled via Software to – RMII Media-Independent InterfaceSave Power– Management Da ..
TMS320C6746BZWT3 ,Fixed/Floating Point Digital Signal Processor 361-NFBGA 0 to 90 SPRS591F–NOVEMBER 2009–REVISED JANUARY 20171.2 Applications• Currency Inspection • Machine Vision ..
TMS320C6746BZWT4 ,Fixed/Floating Point Digital Signal Processor 361-NFBGA 0 to 90• Programmable Real-Time Unit Subsystem • Video Port Interface (VPIF):(PRUSS)– Two 8-Bit SD (BT.656 ..
TMS320C6746BZWTA3 ,Fixed/Floating Point Digital Signal Processor 361-NFBGA -40 to 105Features – Fixed-Point Multiply Supports Two 32 × 32-Bit Multiplies, Four 16 × 16-Bit Multiplies, o ..
TMS320C6747BZKB3 ,Fixed/Floating-Point Digital Signal Processor 256-BGA 0 to 90Features– Hardware Support for Modulo Loop– Superset of the C67x+ and C64x+ ISAsOperation– Up to 36 ..
TMS320C6747BZKBA3 ,Fixed/Floating-Point Digital Signal Processor 256-BGA -40 to 105 SPRS377F–SEPTEMBER 2008–REVISED JUNE 2014The peripheral set includes: a 10/100 Mbps Ethernet MAC ( ..
TPS51620 ,Dual Phase D-CAP+?Mode Step Down Controller for IMVP6+ CPU/GPU Vcore 40-VQFN -10 to 100
TPS51621RHAR ,Dual Phase, D-CAP+?Mode Step-Down Controller for IMVP6.5 CPU/GPU Vcore 40-VQFN -10 to 105
TPS51621RHAT ,Dual Phase, D-CAP+?Mode Step-Down Controller for IMVP6.5 CPU/GPU Vcore 40-VQFN -10 to 105
TPS51631RSMR ,3-phase DCAP+ Step-Down Controller for VR12.5 CPUs 32-VQFN -40 to 105
TPS51631RSMT ,3-phase DCAP+ Step-Down Controller for VR12.5 CPUs 32-VQFN -40 to 105
TPS51727RHAR ,Dual-Phase, D-CAP+? Mode Step Down Power Management IC for 50A+ Applications 40-VQFN -10 to 100maximum ratings" may cause permanent damage to the device. These are stress ratingsonly and functio ..
TMS320C6745BPTP3
Fixed/Floating-Point Digital Signal Processor
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TMS320C6745, TMS320C6747
www.ti.com SPRS377F–SEPTEMBER 2008–REVISED JUNE 2014
TMS320C6745, TMS320C6747 Fixed- and Floating-Point Digital Signal Processor TMS320C6745, TMS320C6747 Fixed- and Floating-Point Digital Signal Processor
1.1 FeaturesBit Multiplies, Four16x 16-Bit Multiplies,or• Software Support Eight8x 8-Bit Multiplies per Clock Cycle,– TI DSP/BIOS™ and Complex Multiples– Chip Support Library and DSP Library – Instruction Packing Reduces Code Size• 375- and 456-MHz TMS320C674x VLIW DSP – All Instructions Conditional• C674x Instruction Set Features – Hardware Supportfor Modulo Loop– Supersetof the C67x+ and C64x+ ISAs Operation– Upto 3648 MIPS and 2736 MFLOPS C674x – Protected Mode Operation– Byte-Addressable (8-, 16-, 32-, and 64-Bit Data) – Exceptions Support for Error Detection and– 8-Bit Overflow Protection Program Redirection– Bit-Field Extract, Set, Clear • 128KBof RAM Shared Memory (TMS320C6747– Normalization, Saturation, Bit-Counting Only) Compact 16-Bit Instructions • 3.3-V LVCMOS I/Os (Exceptfor USB Interfaces) C674x Two-Level Cache Memory Architecture • Two External Memory Interfaces: 32KBof L1P Program RAM/Cache – EMIFA 32KBof L1D Data RAM/Cache • NOR (8-or 16-Bit-Wide Data) 256KBofL2 Unified Mapped RAM/Cache • NAND (8-or 16-Bit-Wide Data) Flexible RAM/Cache Partition (L1 and L2) • 16-Bit SDRAM with 128-MB Address Space Enhanced Direct Memory Access Controller3 (TMS320C6747 Only)
(EDMA3): – EMIFB–2 Transfer Controllers • 32-Bitor 16-Bit SDRAM with 256-MB 32 Independent DMA Channels Address Space (TMS320C6747)8 Quick DMA Channels • 16-Bit SDRAM with 128-MB Address Space
(TMS320C6745)– Programmable Transfer Burst Size Three Configurable 16550-Type UART Modules:• TMS320C674x Fixed- and Floating-Point VLIW
DSP Core – UART0 with Modem Control Signals Load-Store Architecture with Nonaligned – Autoflow Control Signals (CTS, RTS)on UART0
Support Only 64 General-Purpose Registers (32-Bit) – 16-Byte FIFO Six ALU (32- and 40-Bit) Functional Units – 16xor 13x Oversampling Option Supports 32-Bit Integer, SP (IEEE Single • LCD Controller (TMS320C6747 Only)
Precision/32-Bit) and DP (IEEE Double • Two Serial Peripheral Interfaces (SPIs) Each withPrecision/64-Bit) Floating Point One Chip Selectto Four SP Additions Per Clock, • Multimedia Card (MMC)/Secure Digital (SD) Card Every2 Clocks Interface with Secure Data I/O (SDIO) Two Floating-Point (SPor • Two Master and Slave Inter-Integrated Circuit(I2C (RCPxP) Bus™) One Host-Port Interface (HPI) with 16-Bit-Wide Cycle Address/Data Bus Point Multiply • Programmable Real-Time
