TMS320C6713BPYP200 ,Floating-Point Digital Signal Processor SPRS294B − OCTOBER 2005 − REVISED JUNE 2006 Highest ..
TMS320C6713BPYPA200 , FLOATING-POINT DIGITAL SIGNAL PROCESSORS
TMS320C6713BZDP225 ,Floating-Point Digital Signal Processors 272-BGA maximum ratings over operating casedevice characteristics . . . . . . . . . . . . . . . . . . . . . ..
TMS320C6713BZDP300 ,Floating-Point Digital Signal Processors 272-BGA Features2− Native Instructions for IEEE 754 Two Inter-Integrated Circuit Bus (I C Bus)− Single ..
TMS320C6713BZDPA200 , FLOATING-POINT DIGITAL SIGNAL PROCESSORS
TMS320C6713GDP225 ,Floating-Point Digital Signal Processor
TPS51511RHLR ,Synchronous Switcher Controller with 2A LDO for GPU Power 20-VQFN -40 to 85ELECTRICAL CHARACTERISTICSover operating free-air temperature range, V = 5 V (unless otherwise note ..
TPS51511RHLT ,Synchronous Switcher Controller with 2A LDO for GPU Power 20-VQFN -40 to 85FEATURES – Optional PGOOD• Switcher Controller: – Output Discharge– Adjustable-Output Buck Converte ..
TPS51518RUKR ,Single Phase D-CAP and D-CAP2 Controller with 2-bit Flexible VID Controller 20-WQFN -10 to 105 SLUSAO8–DECEMBER 2011(1)(2)RECOMMENDED OPERATING CONDITIONSVALUEMIN MAX UNITSupply voltage V5IN 4. ..
TPS51518RUKR ,Single Phase D-CAP and D-CAP2 Controller with 2-bit Flexible VID Controller 20-WQFN -10 to 105FEATURES APPLICATIONS2• Differential Voltage Feedback• Notebook Computers• DC Compensation for Accu ..
TPS51518RUKT ,Single Phase D-CAP and D-CAP2 Controller with 2-bit Flexible VID Controller 20-WQFN -10 to 105This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated cir ..
TPS51601ADRBR ,Dual High-Efficiency Synchronous MOSFET Driver 8-SON -40 to 105MAXIMUM RATINGSMIN MAX UNITVDD -0.3 6Input voltage VPWM, SKIP -0.3 6BST to SW -0.3 6DRVH to SW -0.3 ..
TMS320C6713BGDP225-TMS320C6713BGDP300-TMS320C6713BGDP-300-TMS320C6713BPYP200-TMS320C6713BZDP225-TMS320C6713BZDP300-TMS32C6713BGDPA200-TMS32C6713BPYPA167
Floating-Point Digital Signal Processor
225-, 200-, 167-MHz (PYP) Clock Rates
− 3.3-, 4.4-, 5-, 6-Instruction Cycle Times
− 2400/1800, 1800/1350, 1600/1200, and
1336/1000 MIPS/MFLOPS
− Rich Peripheral Set, Optimized for Audio
− Highly Optimized C/C++ Compiler
− Extended Temperature Devices Available Advanced Very Long Instruction Word
(VLIW) TMS320C67x DSP Core
− Eight Independent Functional Units:
− 2 ALUs (Fixed-Point)
− 4 ALUs (Floating-/Fixed-Point)
− 2 Multipliers (Floating-/Fixed-Point)
− Load-Store Architecture With 32 32-Bit
General-Purpose Registers
− Instruction Packing Reduces Code Size
− All Instructions Conditional Instruction Set Features
− Native Instructions for IEEE 754
− Single- and Double-Precision
− Byte-Addressable (8-, 16-, 32-Bit Data)
− 8-Bit Overflow Protection
− Saturation; Bit-Field Extract, Set, Clear;
Bit-Counting; Normalization L1/L2 Memory Architecture
− 4K-Byte L1P Program Cache
(Direct-Mapped)
− 4K-Byte L1D Data Cache (2-Way)
− 256K-Byte L2 Memory Total: 64K-Byte
L2 Unified Cache/Mapped RAM, and
192K-Byte Additional L2 Mapped RAM Device Configuration
− Boot Mode: HPI, 8-, 16-, 32-Bit ROM Boot
− Endianness: Little Endian, Big Endian 32-Bit External Memory Interface (EMIF)
− Glueless Interface to SRAM, EPROM,
Flash, SBSRAM, and SDRAM
− 512M-Byte Total Addressable External
Memory Space Enhanced Direct-Memory-Access (EDMA)
Individually Assignable to any of the
Clock Zones
− Each Clock Zone Includes:
− Programmable Clock Generator
− Programmable Frame Sync Generator
− TDM Streams From 2-32 Time Slots
− Support for Slot Size:
8, 12, 16, 20, 24, 28, 32 Bits
− Data Formatter for Bit Manipulation
− Wide Variety of I2S and Similar Bit
Stream Formats
− Integrated Digital Audio Interface
Transmitter (DIT) Supports:
− S/PDIF, IEC60958-1, AES-3, CP-430
Formats
− Up to 16 transmit pins
− Enhanced Channel Status/User Data
− Extensive Error Checking and Recovery Two Inter-Integrated Circuit Bus (I2 C Bus)
Multi-Master and Slave Interfaces Two Multichannel Buffered Serial Ports:
− Serial-Peripheral-Interface (SPI)
− High-Speed TDM Interface
− AC97 Interface Two 32-Bit General-Purpose Timers Dedicated GPIO Module With 16 pins
(External Interrupt Capable) Flexible Phase-Locked-Loop (PLL) Based
Clock Generator Module IEEE-1149.1 (JTAG†)
Boundary-Scan-Compatible 208-Pin PowerPAD PQFP (PYP) 272-BGA Packages (GDP and ZDP) 0.13-µm/6-Level Copper Metal Process
− CMOS Technology 3.3-V I/Os, 1.2‡ -V Internal (GDP/ZDP/ PYP) 3.3-V I/Os, 1.4-V Internal (GDP/ZDP) [300
MHz]All trademarks are the property of their respective owners.† IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.‡
