TMS320C6711DGDP250 ,Floating-Point DSP [Revision D Recommended for New Designs]FeaturesClock Generator Module− Hardware Support for IEEE A Dedicated General-Purpose Input/Outpu ..
TMS320C6711DZDP200 ,Floating-Point Digital Signal Processors 272-BGA 0 to 90electrical characteristics over recommended ranges ofCPU (DSP core) description . . . . . . . . . . ..
TMS320C6711GFN , FLOATING-POINT DIGITAL SIGNAL PROCESSORS
TMS320C6711GFN-150 , FLOATING-POINT DIGITAL SIGNAL PROCESSORS
TMS320C6712DZDP150 ,Floating-Point Digital Signal Processors 272-BGA FeaturesClockGeneratorModule-- HardwareSupportforIEEED ADedicatedGeneral-PurposeInput/OutputSingle- ..
TMS320C6713BGDP225 ,Floating-Point Digital Signal Processor SPRS294B − OCTOBER 2005 − REVISED JUNE 2006 Highest ..
TPS51427A ,Dual D-CAP?Mode Synchronous Step Down Controller for Notebook Power with OOB Function Disabled 32-VQFN -40 to 85features a low-dropout (LDO) regulator that provides– 0.7 V to 5.9 V (Channel1)a 5-V/3.3-V output, ..
TPS51427ARHBR ,Dual D-CAP?Mode Synchronous Step Down Controller for Notebook Power with OOB Function Disabled 32-VQFN -40 to 85maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functio ..
TPS51427ARHBRG4 , DUAL D-CAP™ SYNCHRONOUS STEP-DOWN CONTROLLER FOR NOTEBOOK POWER RAILS
TPS51427ARHBT ,Dual D-CAP?Mode Synchronous Step Down Controller for Notebook Power with OOB Function Disabled 32-VQFN -40 to 85FEATURES DESCRIPTION23• Fixed-Frequency Emulated On-Time Control;The TPS51427A is a dual synchronou ..
TPS51427RHBR ,Dual D-CAP?Mode Synchronous Step Down Controller for Notebook Power Rails 32-VQFN -40 to 85maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functio ..
TPS51427RHBT ,Dual D-CAP?Mode Synchronous Step Down Controller for Notebook Power Rails 32-VQFN -40 to 85FEATURESDESCRIPTION23• Fixed-Frequency Emulated On-Time Control;Frequency Selectable from Three Opt ..
TMS320C6711DGDP200-TMS320C6711DGDP250-TMS320C6711DZDP200
Floating-Point DSP [Revision D Recommended for New Designs]
− 6-, 5-, 4-ns Instruction Cycle Time
− 1000, 1200, 1500 MFLOPS Advanced Very Long Instruction Word
(VLIW) C67x DSP Core
− Eight Highly Independent Functional
Units:
− Four ALUs (Floating- and Fixed-Point)
− Two ALUs (Fixed-Point)
− Two Multipliers (Floating- and
Fixed-Point)
− Load-Store Architecture With 32 32-Bit
General-Purpose Registers
− Instruction Packing Reduces Code Size
− All Instructions Conditional Instruction Set Features
− Hardware Support for IEEE
Single-Precision and Double-Precision
Instructions
− Byte-Addressable (8-, 16-, 32-Bit Data)
− 8-Bit Overflow Protection
− Saturation
− Bit-Field Extract, Set, Clear
− Bit-Counting
− Normalization L1/L2 Memory Architecture
− 32K-Bit (4K-Byte) L1P Program Cache
(Direct Mapped)
− 32K-Bit (4K-Byte) L1D Data Cache
(2-Way Set-Associative)
− 512K-Bit (64K-Byte) L2 Unified Mapped
RAM/Cache
(Flexible Data/Program Allocation) Device Configuration
− Boot Mode: HPI, 8-, 16-, 32-Bit ROM Boot
− Endianness: Little Endian, Big Endian Enhanced Direct-Memory-Access (EDMA)
Controller (16 Independent Channels)
− 256M-Byte Total Addressable External
Memory Space 16-Bit Host-Port Interface (HPI) Two Multichannel Buffered Serial Ports
(McBSPs)
− Direct Interface to T1/E1, MVIP, SCSA
Framers
− ST-Bus-Switching Compatible
− Up to 256 Channels Each
− AC97-Compatible
− Serial-Peripheral-Interface (SPI)
Compatible (Motorola) Two 32-Bit General-Purpose Timers Flexible Software Configurable PLL-Based
Clock Generator Module A Dedicated General-Purpose Input/Output
(GPIO) Module With 5 Pins IEEE-1149.1 (JTAG†)
Boundary-Scan-Compatible 272-Pin Ball Grid Array (BGA) Package
(GDP and ZDP Suffixes) CMOS Technology
− 0.13-µm/6-Level Copper Metal Process 3.3-V I/O, 1.4-V Internal (−250) 3.3-V I/O, 1.20-V Internal ‡
All trademarks are the property of their respective owners.† IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
