TMS320C6455BZTZ , Fixed-Point Digital Signal Processor SPRS276M –MAY 2005–REVISED MARCH 2012TMS320C6455 Fixed-Point Digital Signal ProcessorCheck for Sam ..
TMS320C6455BZTZ2 , Fixed-Point Digital Signal ProcessorFeatures12– 1.25-, 2.5-, 3.125-Gbps Link Rates• High-Performance Fixed-Point DSP (C6455)– Message P ..
TMS320C6455-BZTZ7 , Fixed-Point Digital Signal Processor SPRS276M –MAY 2005–REVISED MARCH 2012The C6455 DSP integrates a large amount of on-chip memory org ..
TMS320C6455BZTZA , Fixed-Point Digital Signal Processor1.1 CTZ/GTZ/ZTZ BGA Package (Bottom View)Figure 1-1 shows the TMS320C6455 device 697-pin ball grid ..
TMS320C6474FZUNA , Multicore Digital Signal Processor SPRS552H–OCTOBER 2008–REVISED APRIL 20111.2 DescriptionThe TMS320C64x+ DSPs (including the TMS320C ..
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TPS5124DBTRG4 ,TPS5124 Dual Channel Synchronous Step-Down PWM ControllerMAXIMUM RATINGS(1)−40°C ≤ T ≤ 85°C, all voltage values are with respect to the network ground term ..
TPS51275CRUKT ,Dual Synchronous, Step-Down Controller with 5-V and 3.3-V LDOs 20-WQFN -40 to 125FEATURES APPLICATIONS2• Input Voltage Range: 5 V to 24 V • Notebook Computers• Output Voltages: 5 V ..
TPS5130 ,Triple Synchronous Buck Controller with LDO Controllerfeatures dead-time control 5-V and 3.3-V Linear Regulators and very low quiescent current.VINVINOU ..
TPS5130PT ,Triple Synchronous Buck Controller with LDO ControllerELECTRICAL CHARACTERISTICSover operating free-air temperature range, V = V = V = 12 V (unless other ..
TPS5130PTR ,Triple Synchronous Buck Controller with LDO ControllerMAXIMUM RATINGS(1)over operating free-air temperature range unless otherwise notedTPS5130(2)Supply ..
TPS5130PTRG4 ,Triple Synchronous Buck Controller with LDO ControllerFEATURES APPLICATIONS Notebook PCs, PDAs Three Independent Step-Down DC/DC Consumer Game Systems ..
TMS320C6455BCTZ-TMS320C6455BCTZA-TMS320C6455BZTZ-TMS320C6455BZTZ2-TMS320C6455-BZTZ7-TMS320C6455BZTZA
Fixed-Point Digital Signal Processor
TMS320C6455
www.ti.com SPRS276M –MAY 2005–REVISED MARCH 2012
TMS320C6455 Fixed-Point Digital Signal Processor
Checkfor Samples: TMS320C6455 Features 1.25-, 2.5-, 3.125-Gbps Link Rates• High-Performance Fixed-Point DSP (C6455) Message Passing, DirectIO Support, Error– 1.39-, 1.17-,1-, 0.83-ns Instruction Cycle Mgmt Extensions, Congestion ControlTime IEEE 1149.6 Compliant I/Os– 720-MHz, 850-MHz, 1-GHz, 1.2-GHz Clock
Rate • DDR2 Memory Controller Eight 32-Bit Instructions/Cycle – Interfacesto DDR2-533 SDRAM 9600 MIPS/MMACS (16-Bits) – 32-Bit/16-Bit, 533-MHz (data rate) Bus Commercial Temperature [0°Cto 90°C] – 512M-Byte Total Addressable External
Memory Space– Extended Temperature [-40°Cto 105°C] EDMA3 Controller (64 Independent Channels)• TMS320C64x+™ DSP Core 32-/16-Bit Host-Port Interface (HPI)– Dedicated SPLOOP Instruction 32-Bit 33-/66-MHz, 3.3-V Peripheral Component– Compact Instructions (16-Bit) Interconnect (PCI) Master/Slave Interface– Instruction Set Enhancements Conformsto PCI Local Bus Specification (v2.3)– Exception Handling • One Inter-Integrated Circuit(I2C) Bus• TMS320C64x+ Megamodule L1/L2 Memory • Two McBSPsArchitecture: • 10/100/1000 Mb/s Ethernet MAC (EMAC)– 256K-Bit (32K-Byte) L1P Program Cache IEEE 802.3 Compliant[Direct Mapped] Supports Multiple Media Independent– 256K-Bit (32K-Byte) L1D Data Cache Interfaces (MII, GMII, RMII, and RGMII)[2-Way Set-Associative]8 Independent Transmit (TX) and– 16M-Bit (2048K-Byte)L2 Unified Mapped 8 Independent Receive (RX) ChannelsRAM/Cache [Flexible Allocation] Two 64-Bit General-Purpose Timers,– 256K-Bit (32K-Byte) L2 ROM Configurableas Four 32-Bit Timers– Time Stamp Counter • UTOPIA• Enhanced Viterbi Decoder Coprocessor (VCP2) UTOPIA Level2 Slave ATM Controller– Supports Over 694 7.95-Kbps AMR – 8-Bit Transmit and Receive Operations upto– Programmable Code Parameters 50 MHz per Direction• Enhanced Turbo Decoder Coprocessor (TCP2) – User-Defined Cell Format upto64 Bytes 2-Mbps 3GPP • 16 General-Purpose I/O (GPIO) Pins • System PLL and PLL Controller and Decoding Secondary PLL and PLL Controller, Dedicated Memory Controller (AET) Compatible • Trace-Enabled • IEEE-1149.1 (JTAG™) and CompatibleSynchronous ZBT • 697-Pin Ball Grid Array (BGA) Package
(CTZ, GTZ,or ZTZ 0.8-mm Sync Devices • 0.09-μm/7-Level • 3.3-/1.8-/1.5-/1.25-/1.2-V External 1.25-/1.2-V Internal (or One 4x),
