TMS320C6424ZWT7 ,Fixed-Point Digital Signal Processor 361-NFBGA 0 to 90• 10/100 Mb/s Ethernet MAC (EMAC) • Packages:– IEEE 802.3 Compliant – 361-Pin Pb-Free PBGA Package( ..
TMS320C6454BZTZ , Fixed-Point Digital Signal ProcessorFeatures12– Interfaces to DDR2-533 SDRAM• High-Performance Fixed-Point DSP (C6454)– 32-Bit/16-Bit, ..
TMS320C6455BCTZ ,Fixed-Point Digital Signal Processor 697-FCBGA 0 to 90block diagram of the C6455 device.C645532DDR2DDR2 SDRAMMem CtlrPLL2 andSBSRAMPLL2(D)ControllerZBT S ..
TMS320C6455BCTZA ,Fixed-Point Digital Signal Processor 697-FCBGA -40 to 105Features Copyright 2005–2012, Texas Instruments IncorporatedSubmit Documentation FeedbackProduct F ..
TMS320C6455BZTZ , Fixed-Point Digital Signal Processor SPRS276M –MAY 2005–REVISED MARCH 2012TMS320C6455 Fixed-Point Digital Signal ProcessorCheck for Sam ..
TMS320C6455BZTZ2 , Fixed-Point Digital Signal ProcessorFeatures12– 1.25-, 2.5-, 3.125-Gbps Link Rates• High-Performance Fixed-Point DSP (C6455)– Message P ..
TPS5124DBTG4 ,TPS5124 Dual Channel Synchronous Step-Down PWM Controller 30-TSSOP -40 to 85ELECTRICAL CHARACTERISTICS T = −40°C to 85°C, V = 12 V (unless otherwise noted)J CCPARAMETER TEST C ..
TPS5124DBTR ,TPS5124 Dual Channel Synchronous Step-Down PWM Controllerfeatures such as Consumer Game Systemsundervoltage lockout, overvoltage, undervoltage,and programm ..
TPS5124DBTRG4 ,TPS5124 Dual Channel Synchronous Step-Down PWM ControllerMAXIMUM RATINGS(1)−40°C ≤ T ≤ 85°C, all voltage values are with respect to the network ground term ..
TPS51275CRUKT ,Dual Synchronous, Step-Down Controller with 5-V and 3.3-V LDOs 20-WQFN -40 to 125FEATURES APPLICATIONS2• Input Voltage Range: 5 V to 24 V • Notebook Computers• Output Voltages: 5 V ..
TPS5130 ,Triple Synchronous Buck Controller with LDO Controllerfeatures dead-time control 5-V and 3.3-V Linear Regulators and very low quiescent current.VINVINOU ..
TPS5130PT ,Triple Synchronous Buck Controller with LDO ControllerELECTRICAL CHARACTERISTICSover operating free-air temperature range, V = V = V = 12 V (unless other ..
TMS320C6424ZDU4-TMS320C6424ZWT7
Fixed-Point Digital Signal Processor
TMS320C6424
www.ti.com SPRS347D–MARCH 2007–REVISED DECEMBER 2009
TMS320C6424 Fixed-Point Digital Signal Processor
Checkfor Samples: TMS320C6424 TMS320C6424 Fixed-Point Digital Signal Processor
1.1 Features High-Performance Digital Signal Processor • C64x+ L1/L2 Memory Architecture
(C6424) – 256K-Bit (32K-Byte) L1P Program 2.5-, 2-, 1.67-, 1.43-ns Instruction Cycle Time RAM/Cache [Flexible Allocation] 400-, 500-, 600-, 700-MHz C64x+™ Clock Rate – 640K-Bit (80K-Byte) L1D Data RAM/Cache
[Flexible Allocation]– Eight 32-Bit C64x+ Instructions/Cycle 1M-Bit (128K-Byte)L2 Unified Mapped– 3200, 4000, 4800, 5600 MIPS RAM/Cache [Flexible Allocation]– Fully Software-Compatible With C64x • Endianess: Supports Both Little Endian and– Commercial and Automotive (QorS suffix) Big EndianGrades • External Memory Interfaces (EMIFs)– Low-Power Device(L suffix) – 32-Bit DDR2 SDRAM Memory Controller With• VelociTI.2™ Extensionsto VelociTI™ 256M-Byte Address Space (1.8-V I/O)Advanced Very-Long-Instruction-Word (VLIW) Supports upto 333-MHz (data rate) busTMS320C64x+™ DSP Core
and interfacesto DDR2-400 SDRAM– Eight Highly Independent Functional Units – Asynchronous 16-Bit Wide EMIF (EMIFA)With VelociTI.2 Extensions: With upto 128M-Byte Address Reach• Six ALUs (32-/40-Bit), Each Supports • Flash Memory InterfacesSingle 32-Bit, Dual 16-Bit,or Quad 8-Bit
Arithmetic per Clock Cycle – NOR (8-/16-Bit-Wide Data) Two Multipliers Support Four16x 16-Bit – NAND (8-/16-Bit-Wide Data)
Multiplies (32-Bit Results) per Clock • Enhanced Direct-Memory-Access (EDMA)Cycleor Eight8x 8-Bit Multiplies (16-Bit Controller (64 Independent Channels)Results) per Clock Cycle • Two 64-Bit General-Purpose Timers (Each Load-Store Architecture With Non-Aligned Configurableas Two 32-Bit Timers)
Support • One 64-Bit Watch Dog Timer– 64 32-Bit General-Purpose Registers • Two UARTs (One with RTS and CTS Flow– Instruction Packing Reduces Code Size Control) All Instructions Conditional • Master/Slave Inter-Integrated Circuit(I2C Bus™) Enhancements • Two Multichannel Buffered Serial Ports Operation (McBSPs) Error Detection – I2S and TDM Interface – Standard Voice – Telecom Interfaces Data) – 128 Channel Mode • Multichannel Audio Serial Port (McASP0) – Four Serializers SPDIF (DIT) • 16-Bit Host-Port • 32-Bit 33-MHz, Component Interconnect (PCI) Master/Slave Interface Support
