TMS320C6414TBGLZ7 ,Fixed-Point Digital Signal Processor 532-FCBGA 0 to 90maximum ratings over operating casetemperature range . . . . . . . . . . . . . . . . . . . . . . . ..
TMS320C6414TBGLZA6 ,Fixed-Point Digital Signal Processor 532-FCBGA -40 to 105 SPRS226M − NOVEMBER 2003 − ..
TMS320C6414TBZLZ8 ,Fixed-Point Digital Signal Processor 532-FCBGA 0 to 90maximum ratings over operating casetemperature range . . . . . . . . . . . . . . . . . . . . . . . ..
TMS320C6414TBZLZA6 ,Fixed-Point Digital Signal Processor 532-FCBGA -40 to 105Features− ST-Bus-Switching-, AC97-Compatible− Byte-Addressable (8-/16-/32-/64-Bit Data)− Serial ..
TMS320C6414TBZLZA8 ,Fixed-Point Digital Signal Processor 532-FCBGA -40 to 105 SPRS226M − NOVEMBER 2003 − ..
TMS320C6414TGLZA8 , FIXED-POINT DIGITAL SIGNAL PROCESSORS
TPS51125RGER ,Dual-Synchronous, Step-Down Controller with Out-of-AudioT Operation and 100-mA LDOs 24-VQFN -40 to 85Sample & Support &Product Tools &TechnicalCommunityBuyFolder Documents SoftwareTPS51125SLUS786H–OCT ..
TPS51125RGET ,Dual-Synchronous, Step-Down Controller with Out-of-AudioT Operation and 100-mA LDOs 24-VQFN -40 to 85Block Diagram... 15Information..... 304 Revision HistoryNOTE: Page numbers for previous revisions m ..
TPS51125RGET ,Dual-Synchronous, Step-Down Controller with Out-of-AudioT Operation and 100-mA LDOs 24-VQFN -40 to 85Features 3 DescriptionThe TPS51125 is a cost-effective, dual-synchronous1• Wide Input Voltage Range ..
TPS51125RGETG4 ,Dual-Synchronous, Step-Down Controller with Out-of-AudioT Operation and 100-mA LDOs 24-VQFN -40 to 85Features... 17.4 Device Functional Modes.... 222 Applications..... 18 Application and Implementatio ..
TPS51163DRCR ,4.5V to 13.2V Synchronous Buck Controller with High Current Gate Driver, 600kHz 10-VSON -40 to 85FEATURES DESCRIPTION• Flexible Power Rails: 5 V to 12 VThe TPS51113 and TPS51163 are cost-optimized ..
TPS5120 ,Dual Output, Two-Phase Synchronous Buck Controller with Wide Input Voltage Rangefeatures, such as undervoltage lockout, power good, overvoltage,undervoltage, and programmable shor ..
TMS320C6414TBGLZ1-TMS320C6414TBGLZ7-TMS320C6414TBGLZA6-TMS320C6414TBZLZ8-TMS320C6414TBZLZA6-TMS320C6414TBZLZA8-TMS320C6414TZLZ1-TMS320C6414TZLZ6-TMS320C6414TZLZ7-TMS320C6414TZLZA6
Fixed-Point Digital Signal Processor
− 4800, 5760, 6800, 8000 MIPS
− Fully Software-Compatible With C62x
− C6414/15/16 Devices Pin-Compatible
− Extended Temperature Devices Available VelociTI.2 Extensions to VelociTI
Advanced Very-Long-Instruction-Word
(VLIW) TMS320C64x DSP Core
− Eight Highly Independent Functional
Units With VelociTI.2 Extensions:
− Six ALUs (32-/40-Bit), Each Supports
Single 32-Bit, Dual 16-Bit, or Quad
8-Bit Arithmetic per Clock Cycle
− Two Multipliers Support
Four 16 x 16-Bit Multiplies
(32-Bit Results) per Clock Cycle or
Eight 8 x 8-Bit Multiplies
(16-Bit Results) per Clock Cycle
− Non-Aligned Load-Store Architecture
− 64 32-Bit General-Purpose Registers
− Instruction Packing Reduces Code Size
− All Instructions Conditional Instruction Set Features
− Byte-Addressable (8-/16-/32-/64-Bit Data)
− 8-Bit Overflow Protection
− Bit-Field Extract, Set, Clear
− Normalization, Saturation, Bit-Counting
− VelociTI.2 Increased Orthogonality VCP [C6416T Only]
− Supports Over 833 7.95-Kbps AMR
− Programmable Code Parameters TCP [C6416T Only]
− Supports up to 10 2-Mbps or
60 384-Kbps 3GPP (6 Iterations)
− Programmable Turbo Code and
Decoding Parameters L1/L2 Memory Architecture
− 128K-Bit (16K-Byte) L1P Program Cache
(Direct Mapped)
− 128K-Bit (16K-Byte) L1D Data Cache
(2-Way Set-Associative)
− 8M-Bit (1024K-Byte) L2 Unified Mapped
SBSRAM, ZBT SRAM, and FIFO)
− 1280M-Byte Total Addressable External
Memory Space Enhanced Direct-Memory-Access (EDMA)
Controller (64 Independent Channels) Host-Port Interface (HPI)
− User-Configurable Bus Width (32-/16-Bit) 32-Bit/33-MHz, 3.3-V PCI Master/Slave
Interface Conforms to PCI Specification 2.2
[C6415T/C6416T]
− Three PCI Bus Address Registers:
Prefetchable Memory
Non-Prefetchable Memory I/O
− Four-Wire Serial EEPROM Interface
− PCI Interrupt Request Under DSP
Program Control
− DSP Interrupt Via PCI I/O Cycle Three Multichannel Buffered Serial Ports
− Direct Interface to T1/E1, MVIP, SCSA
Framers
− Up to 256 Channels Each
− ST-Bus-Switching-, AC97-Compatible
− Serial Peripheral Interface (SPI)
Compatible (Motorola) Three 32-Bit General-Purpose Timers UTOPIA [C6415T/C6416T]
− UTOPIA Level 2 Slave ATM Controller
− 8-Bit Transmit and Receive Operations
up to 50 MHz per Direction
− User-Defined Cell Format up to 64 Bytes Sixteen General-Purpose I/O (GPIO) Pins Flexible PLL Clock Generator IEEE-1149.1 (JTAG†)
Boundary-Scan-Compatible 532-Pin Ball Grid Array (BGA) Package
(GLZ/ZLZ/CLZ Suffixes), 0.8-mm Ball Pitch 0.09-µm/7-Level Cu Metal Process (CMOS) 3.3-V I/Os, 1.1-V Internal (600 MHz) 3.3-V I/Os, 1.2-V Internal (720/850 MHZ, 1 †IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
