TMS320C6211BGFN150 ,Fixed-Point Digital Signal ProcessorFeatures− Up to 256 Channels Each− Byte-Addressable (8-, 16-, 32-Bit Data)− AC97-Compatible− 8- ..
TMS320C6211BGFN180 ,Fixed-Point Digital Signal Processor 256-BGA maximum ratings over operating casetemperature range . . . . . . . . . . . . . . . . . . . . . . . ..
TMS320C6211BZFN167 ,Fixed-Point Digital Signal Processor 256-BGA SPRS073L − AUGUST 1998 − REVISED JUNE 2005 ..
TMS320C6410GTS400 ,Fixed-Point Digital Signal ProcessorFunctional Description for 11 to “EMIFA 8−bit ROM boot”55 Device Configurations, Device Status Regi ..
TMS320C6410ZTS400 ,Fixed-Point Digital Signal Processor 288-FCBGA Features, 32−Bit External Memory Interface (EMIF) section:Changed “1024M−Byte Total Addressable Mem ..
TMS320C6410ZTSA400 ,Fixed-Point Digital Signal Processor 288-FCBGA TMS320C6413, TMS320C6410Fixed-Point Digital SignalProcessorsData ManualLiterature Number: SPRS247FA ..
TPS51117PWR ,1.8V to 28V Input Sync. Step Down Controller with DCAP? Mode, Optimized for Light Load Efficiency 14-TSSOP -40 to 85Features... 18.2 Typical Application..... 162 Applications..... 18.3 System Examples...... 203 Desc ..
TPS51117PWRG4 ,1.8V to 28V Input Sync. Step Down Controller with DCAP? Mode, Optimized for Light Load Efficiency 14-TSSOP -40 to 85Electrical Characteristics....... 511.1 Device Support 236.4 Typical Characteristics. 711.2 Communi ..
TPS51117RGYR ,1.8V to 28V Input Sync. Step Down Controller with DCAP? Mode, Optimized for Light Load Efficiency 14-VQFN -40 to 85Table of Contents8.1 Application Information........ 161
TPS51117RGYRG4 ,1.8V to 28V Input Sync. Step Down Controller with DCAP? Mode, Optimized for Light Load Efficiency 14-VQFN -40 to 85Features... 18.2 Typical Application..... 162 Applications..... 18.3 System Examples...... 203 Desc ..
TPS51117RGYT ,1.8V to 28V Input Sync. Step Down Controller with DCAP? Mode, Optimized for Light Load Efficiency 14-VQFN -40 to 85Features 3 DescriptionThe TPS51117 device is a cost-effective,1• High Efficiency, Low Power Consump ..
TPS51117RGYT ,1.8V to 28V Input Sync. Step Down Controller with DCAP? Mode, Optimized for Light Load Efficiency 14-VQFN -40 to 85Maximum Ratings . 410.3 Thermal Considerations.... 226.2 Recommended Operating Conditions..... 411 ..
TMS320C6211BGFN150-TMS320C6211BGFN180-TMS320C6211BZFN167
Fixed-Point Digital Signal Processor
Pin-Compatible
− 150-, 167-MHz Clock Rates
− 6.7-, 6-ns Instruction Cycle Time
− 1200, 1333 MIPS
− Extended Temperature Device (C6211B) VelociTI Advanced Very Long Instruction
Word (VLIW) C62x DSP Core (C6211/11B)
− Eight Highly Independent Functional
Units:
− Six ALUs (32-/40-Bit)
− Two 16-Bit Multipliers (32-Bit Results)
− Load-Store Architecture With 32 32-Bit
General-Purpose Registers
− Instruction Packing Reduces Code Size
− All Instructions Conditional Instruction Set Features
− Byte-Addressable (8-, 16-, 32-Bit Data)
− 8-Bit Overflow Protection
− Saturation
− Bit-Field Extract, Set, Clear
− Bit-Counting
− Normalization L1/L2 Memory Architecture
− 32K-Bit (4K-Byte) L1P Program Cache
(Direct Mapped)
− 32K-Bit (4K-Byte) L1D Data Cache
(2-Way Set-Associative)
− 512K-Bit (64K-Byte) L2 Unified Mapped
RAM/Cache
(Flexible Data/Program Allocation)
− Glueless Interface to Asynchronous
Memories: SRAM and EPROM
− Glueless Interface to Synchronous
Memories: SDRAM and SBSRAM
− 512M-Byte Total Addressable External
Memory Space Enhanced Direct-Memory-Access (EDMA)
Controller (16 Independent Channels) 16-Bit Host-Port Interface (HPI)
− Access to Entire Memory Map Two Multichannel Buffered Serial Ports
(McBSPs)
− Direct Interface to T1/E1, MVIP, SCSA
Framers
− ST-Bus-Switching Compatible
− Up to 256 Channels Each
− AC97-Compatible
− Serial-Peripheral-Interface (SPI)
Compatible (Motorola) Two 32-Bit General-Purpose Timers Flexible Phase-Locked-Loop (PLL) Clock
Generator IEEE-1149.1 (JTAG†)
Boundary-Scan-Compatible 256-Pin Ball Grid Array (BGA) Package
(GFN and ZFN Suffixes) 0.18-µm/5-Level Metal Process
− CMOS Technology 3.3-V I/Os, 1.8-V Internal All trademarks are the property of their respective owners.
†IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
