TMS320C6203BGNZ173 ,Fixed-Point Digital Signal ProcessorFeaturesCompatible (Motorola)− Byte-Addressable (8-, 16-, 32-Bit Data)− 8-Bit Overflow Protectio ..
TMS320C6203BZNY173 ,Fixed-Point Digital Signal Processor 384-FC/CSP FeaturesCompatible (Motorola)− Byte-Addressable (8-, 16-, 32-Bit Data)− 8-Bit Overflow Protectio ..
TMS320C6203BZNY300 ,Fixed-Point Digital Signal Processor 384-FC/CSP block diagram . . . . . . . . . 9synchronous-burst memory timing . . . . . . . . . . . . . . . . . ..
TMS320C6204GHK200 ,Fixed-Point Digital Signal ProcessorTMS320C6204FIXED-POINTDIGITALSIGNALPROCESSORSPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004D High-Pe ..
TMS320C6204GHKA200 ,Fixed-Point Digital Signal Processorblock diagram 7synchronous DRAM timing ..... 50CPU (DSP core) description ...... 8memory map summar ..
TMS320C6204GLW200 ,Fixed-Point Digital Signal ProcessorFeaturesCompatible(Motorola™)-- Byte-Addressable(8-,16-,32-BitData)-- 8-BitOverflowProtection D Two ..
TPS51116PWP ,DDR2 Switcher and LDOPin Functions (continued)NO.NAME I/O DESCRIPTIONPWP RGEVTT 2 24 O Power output for the VTT LDO.VTTG ..
TPS51116PWPG4 ,DDR1, DDR2, DDR3 Switcher and LDO 20-HTSSOP -40 to 85Maximum Ratings(1)over operating free-air temperature range (unless otherwise noted)MIN MAX UNITVBS ..
TPS51116PWPR ,DDR2 Switcher and LDOFeatures... 18.4 Device Functional Modes.... 242 Applications..... 19 Application and Implementatio ..
TPS51116PWPRG4 ,DDR2 Switcher and LDOFeatures... 18.4 Device Functional Modes.... 242 Applications..... 19 Application and Implementatio ..
TPS51116RGE , COMPLETE DDR, DDR2 AND DDR3 MEMORY POWER SOLUTION SYNCHRONOUS BUCK CONTROLLER, 3-A LDO, BUFFERED REFERENCE
TPS51116RGER ,DDR1, DDR2, DDR3 Switcher and LDO 24-VQFN -40 to 85Features section.... 1• Added reference to "SSTL-15" in Applications section ...... 1• Added refere ..
TMS320C6203BGNZ173
Fixed-Point Digital Signal Processor
− 2000, 2400 MIPS C6203B and C6202 GLS Ball Grid Array
(BGA) Packages are Pin-Compatible With
the C6204 GLW BGA Package† C6203B and C6202B GNZ, GNY and ZNY
Packages are Pin-Compatible VelociTI Advanced Very-Long-Instruction-
Word (VLIW) C62x DSP Core
− Eight Highly Independent Functional
Units:
− Six ALUs (32-/40-Bit)
− Two 16-Bit Multipliers (32-Bit Result)
− Load-Store Architecture With 32 32-Bit
General-Purpose Registers
− Instruction Packing Reduces Code Size
− All Instructions Conditional Instruction Set Features
− Byte-Addressable (8-, 16-, 32-Bit Data)
− 8-Bit Overflow Protection
− Saturation
− Bit-Field Extract, Set, Clear
− Bit-Counting
− Normalization 7M-Bit On-Chip SRAM
− 3M-Bit Internal Program/Cache
(96K 32-Bit Instructions)
− 4M-Bit Dual-Access Internal Data
(512K Bytes)
− Organized as Two 256K-Byte Blocks
for Improved Concurrency 32-Bit External Memory Interface (EMIF)
− Glueless Interface to Synchronous
Memories: SDRAM or SBSRAM
− Glueless Interface to Asynchronous
Memories: SRAM and EPROM
− 52M-Byte Addressable External Memory
Space 32-Bit Expansion Bus (XBus)
− Glueless/Low-Glue Interface to Popular
PCI Bridge Chips
− Glueless/Low-Glue Interface to Popular
Synchronous or Asynchronous
Microprocessor Buses
− Master/Slave Functionality
− Glueless Interface to Synchronous FIFOs
and Asynchronous Peripherals Three Multichannel Buffered Serial Ports
(McBSPs)
− Direct Interface to T1/E1, MVIP, SCSA
Framers
− ST-Bus-Switching Compatible
− Up to 256 Channels Each
− AC97-Compatible
− Serial-Peripheral Interface (SPI)
Compatible (Motorola) Two 32-Bit General-Purpose Timers IEEE-1149.1 (JTAG‡)
Boundary-Scan-Compatible 352-Pin BGA Package (GNZ) 384-Pin BGA Package (GLS) 384-Pin BGA Packages (GNY and ZNY) 0.15-µm/5-Level Metal Process
− CMOS Technology 3.3-V I/Os, 1.5-V Internal Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TMS320C62x, VelociTI, and C62x are trademarks of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
All trademarks are the property of their respective owners.
†For more details, see the GLS BGA package bottom view.
‡IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
