TMS320C10NL ,Digital Signal Processor 40-PDIP 0 to 0features for each ′C1x DSP.This data sheet is arranged as follows: introduction, quick reference ta ..
TMS320C10NL-25 ,Digital Signal Processor 40-PDIP 0 to 70features for each ′C1x DSP.This data sheet is arranged as follows: introduction, quick reference ta ..
TMS320C15FNL-25 ,Digital Signal Processors 44-PLCC 0 to 70
TMS320C15NL25 , Digital Signal Processors
TMS320C15NL-25 ,Digital Signal Processors 40-PDIP 0 to 70
TMS320C15PEL , Digital Signal Processors
TPS40100RGET ,MIDRANGE INPUT SYNCHRONOUS BUCK CONTROLLER WITH ADVANCED SEQUENCING AND OUTPUT MARGININGMAXIMUM RATINGS(1)over operating free-air temperature range unless otherwise notedTPS40100 UNITVDD ..
TPS40100RGETG4 ,Wide Input Range Synchronous Buck Controller for Sequencing 24-VQFN -40 to 85maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functi ..
TPS40101RGER ,Mid Range Input Synchronous Buck Controller with Advanced Sequencing and Output Margining 24-VQFN -40 to 85Electrical Characteristics 3• Output Voltage Range From 0.69 V to 5.5 V• Simultaneous, Ratiometric ..
TPS40101RGET ,Mid Range Input Synchronous Buck Controller with Advanced Sequencing and Output Margining 24-VQFN -40 to 85ELECTRICAL CHARACTERISTICS-40°C ≤ T = T ≤ 85°C, V = 12 V, R = 182 kΩ, R = 232 kΩ, R = 121 kΩ (unles ..
TPS40120PW ,Programmable Feedback DividerSLUS616B–JULY 2004–REVISED AUGUST 2004DEVICE INFORMATIONPW PACKAGE(TOP VIEW)1VID5 14 VCCVID0 2 NCPU ..
TPS40120PWR ,Programmable Feedback DividerFEATURES DESCRIPTION• VRM 10.x VID Code TableThe TPS40120 is a 6-bit digitally programmedfeedback d ..
TMS320C10FNL-TMS320C10FNL25-TMS320C10FNL-25-TMS320C10NL-TMS320C10NL-25
DIGITAL SIGNAL PROCESSORS
1.5K/4K/8K-Word On-Chip Program ROM 4K-Word On-Chip Program EPROM (TMS320E14/P14/E15/P15/E17/P17) One-Time Programmable (OTP)
Versions Available (TMS320P14/P15/P17) EPROM Code Protection for Copyright
Security 4K / 64K-Word Total External Memory at
Full Speed 32-Bit ALU/Accumulator 16 × 16-Bit Multiplier With a 32-Bit Product 0 to 16-Bit Barrel Shifter Eight Input/Output Channels Dual-Channel Serial Port Simple Memory and I/O Interface 5-V and 3.3-V Versions Available
(TMS320LC15/LC17) Packaging: DIP , PLCC, Quad Flatpack, and
CER-QUAD CMOS Technology:
Device Cycle Time
— TMS320C10 200-ns. . . . . . . . . . . . . . . . . . .
— TMS320C10-14 280-ns. . . . . . . . . . . . . . . .
— TMS320C10-25 160-ns. . . . . . . . . . . . . . . .
— TMS320C14 160-ns. . . . . . . . . . . . . . . . . . .
— TMS320E14 160-ns. . . . . . . . . . . . . . . . . . .
— TMS320P14 160-ns. . . . . . . . . . . . . . . . . . .
— TMS320C15 200-ns. . . . . . . . . . . . . . . . . . .
— TMS320C15-25 160-ns. . . . . . . . . . . . . . . .
— TMS320E15 200-ns. . . . . . . . . . . . . . . . . . .
— TMS320E15-25 160-ns. . . . . . . . . . . . . . . .
— TMS320LC15 250-ns. . . . . . . . . . . . . . . . . .
— TMS320P15 200-ns. . . . . . . . . . . . . . . . . . .
— TMS320C16 114-ns. . . . . . . . . . . . . . . . . . .
— TMS320C17 200-ns. . . . . . . . . . . . . . . . . . .
— TMS320E17 200-ns. . . . . . . . . . . . . . . . . . .
— TMS320LC17 278-ns. . . . . . . . . . . . . . . . . .
— TMS320P17 200-ns. . . . . . . . . . . . . . . . . . . introductionThe TMS32010 digital signal processor (DSP), introduced in 1983, was the first DSP in the TMS320 family. From
it has evolved this TMS320C1x generation of 16-bit DSPs. All ′C1x DSPs are object code compatible with the
TMS32010 DSP. The ′C1x DSPs combine the flexibility of a high-speed controller with the numerical capability
of an array processor, thereby offering an inexpensive alternative to multichip bit-slice processors. The highly
paralleled architecture and efficient instruction set provide speed and flexibility to produce a CMOS
microprocessor generation capable of executing up to 8.77 MIPS (million instructions per second) (′C16). These
′C1x devices utilize a modified Harvard architecture to optimize speed and flexibility, implementing functions in
hardware that other processors implement through microcode or software.
The ′C1x generation’s powerful instruction set, inherent flexibility, high-speed number-handling capabilities,
reduced power consumption, and innovative architecture have made these cost-effective DSPs the ideal
solution for many telecommunications, computer, commercial, industrial, and military applications.
This data sheet provides detailed design documentation for the ′C1x DSPs. It facilitates the selection of devices
best suited for various user applications by providing specifications and special features for each ′C1x DSP.
This data sheet is arranged as follows: introduction, quick reference table of device parameters and packages,
summary overview of each device, architecture overview, and the ′C1x device instruction set summary. These
are followed by data sheets for each ′C1x device providing available package styles, terminal function tables,
block diagrams, and electrical and timing parameters. An index is provided to facilitate data sheet usage.
