TMM23256P ,256K Bit Mask ROMFEATURES0 Single 5V Power Supplyq Fast Access' Time , 150ns (Max.)q Low Power DissipationAverage Cu ..
TMM23256P ,256K Bit Mask ROMTOSHIBA M08 MEMORY PRODUCTS256K BIT (32K WORD X 8 BIT) MASK ROMN-CHANNEL SILICON GATEDESCRIPTIONThe ..
TMM24256BP-20 ,200ns; V(cc): -0.6 to 7V; V; 32,768 x 8-bit one time programmable read only memoryTOSHIBA M08 MEMORY PRODUCTSTllMlli24256BP/BFl 7, '20DESCRIPTIONThe Tyfrf21i256BP/BF is a 32,768 wor ..
TMM6263FILM ,SMALL SIGNAL SCHOTTKY DIODEABSOLUTE MAXIMUM RATINGS (limiting values)Symbol Parameter Value UnitV Repetitive Peak Reverse Volt ..
TMMBAT41 ,SMALL SIGNAL SCHOTTKY DIODETMMBAT 41®SMALL SIGNAL SCHOTTKY DIODEDESCRIPTIONGeneral purpose metal to silicon diode featuringver ..
TMMBAT41FILM ,SMALL SIGNAL SCHOTTKY DIODETMMBAT 41®SMALL SIGNAL SCHOTTKY DIODEDESCRIPTIONGeneral purpose metal to silicon diode featuringver ..
TP3420AJ ,ISDN S/T Interface Devicefeatures for compliance with the new n Selectable TE or NT moderelease of ANSI T1.605-1991 and CCIT ..
TP3420AN308 ,ISDN S/T Interface Devicefeatures.n Clock resynchronizer and elastic buffers for NT-2/LTThe TP3420A S Interface Device (SID™ ..
TP3420AN308 ,ISDN S/T Interface DeviceApplications“B” channels, each of 64 kb/s, and 1 “D” channel at 16 kb/sn Same Device for NT, TE and ..
TP3420AV ,ISDN S/T Interface DevicePin DescriptionsTP3420A SIDName DescriptionGND Negative power supply pin, normally 0V(ground). All ..
TP3420AV308 ,ISDN S/T Interface DeviceFeaturesn 2B+D 4-wire 192 kb/s transceiverThe TP3420A is an enhanced version of the TP3420, with an ..
TP3420AV308 ,ISDN S/T Interface DeviceTP3420A ISDN S/T Interface DevicePRELIMINARYJuly 1994TP3420AISDN S/T Interface Device
TMM23256P
256K Bit Mask ROM
TllDSlHlllIlll ll/‘MDS liiljEliiliiaG PREDEDHMBW
256K BIT (32K WORD X 8 BIT) MASK ROM
N-CHANNEL SILICON GATE
DESCRIPTION
The TMM23256P is a 262,144 bit read only
memory organized as 32,768 words by 8 bits with a
low bit cost, thus being most suitable for use in
character generator.
Consisting of static memory cells and clocked pe-
ripheral circuitry, the TMM23256P provides a high
speed and low power dissipation (access time 150ns,
operating current 40mA).
The TMM23256P also features aro_automatic stand-
by-p9yter mppp, When deselected by Chip Enable
(C_E), iii'd" bperating current is reduced from 40mA to
FEATURES
Single 5V Power Supply
Fast Access' Time , 150ns (Max.)
Low Power Dissipation
Average Current 40mA (Max.)
Standby Current 1 lOmA (Max.)
Inputs protected .' All Inputs have Protection
Against Static Charge
PIN CONNECTION
-u.e-"-'
, N.C.E1 23 :IVCC
"”“15 2 27 3A”
AVE 3 26 JAia
Act: 4 25 3A3
Asl:1 5 24 3A9
Adj 6 23 C1A11
MC 7 (22 - P
A2Ea 2.1.. Atty
Alcg @m,/
AM: 10 19 Do,
Col: 11 " 06
01:12 17 Ds
02C 13 16 304
GNDE: 14 15 Dros
PIN NAMES
Ao ~ A14 Address Inputs
Do -- D, Data Outputs
E Output Enable Input
c7 Chip Enable Input
NC. No Connection
Vcc Power Supply Terminal
GND Ground
TMM23256P
lOmA. Output Enable (OTC) is effective in preventing
data confliction on a common bys line.
The TMM23256P uses the address latch system
that the falling edge of c7 latches all inputs except
for (TE, thus can be easily connected to a system
where address and data buses are commonly used.
The TMM23256P is fabricated with ion implanted
N-channel silicon gate technology. This technology
allows a production on high performance.
The TMM23256P is moulded in a 28 pin standard
plastic package, 0.6 inch in width.
' - - .__ . ,.
0 Edge Enabled Operation . CE
0 Output Buffer Control -. CE
q Input and Output . TTL Compatible
0 Three State Outputs , Wired OR Capability
o 28 pin Standard Plastic DIP
BLOCK DIAGRAM
VCC GND
I I DoD102DsD4Dso6t07
OE''-----------, mm‘ii
Buffers
Chip, E nablo
Input Buffer
and Clock
A0 IF--
Al o---, Column
Decoder
A. Ir---,
IO 512 252,144 bits
\ Memory cell
Aiio---
Air---
Address Input Buffers arid latches
Row Decoder
Ai30----,
TMM23256P
MAXIMUM RATINGS
SYMBOL ITEM RATING UNIT
Vcc Power Supply Voltage -0.5 ' 7.0 , V
VIN, VOUT Input and Output Voltage -Ch5 ' 7.0 V
TOpR Operating Temperature 0 ' 70 °C
TSTRG Storage Temperature -55 PN.. 150 'C
TSOLDER Soldering Temperature . Time 260 . 10 °C . sec
PD Power Dissipation (Ta = 70°C) 1.0 L W
D.C. OPERATING CONDITIONS (Ta=0-- 70'C)
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Ihr., Input High Voltage - 2.2 - Vcc + 1 V
Ihr, Input Low Voltage - --Ch5 - 0.8 V
Vcc Power Supply Voltage - 4.5 5.0 l 5.5 V
D.C. and OPERATING CHARACTERISTICS (Ta = 0 ' 70°C)
SYMBOL PARAMETER CONDITIONS MIN. TYP, MAX. UNIT
' Input High Current N/m: = 5.5V - 0.05 10 pA
IIL I Input Low Current l V|N = GND - -0.05 --IO PA
VOH Output High Voltage lor., = --400PA 2.4 3.3 - V
Var, Output Low Voltage IOL = 3.2mA - 0.3 0.4 V
I v = 5.5V CE = 2.2V or - 0.05 10 A
L0H Output Leakage Current OUT - p
|LOL VOUT = 0.4V ' OE = 2.2V - --0.1 -20 PA
ICC! Standby Current CT = 2.2V - - 10 - mA
. lcce Average Current ICYC = 230ns, lOUT = 0mA - - 40. _ mA
. Tipical values are at Ta = 25°C and Vcc = 5V.
CAPACITANCE (Ta = 25°C, f = 1MHz)
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
CIN Input Capacitance VIN = AC. GND - 5 10 pF
COU-r Output Capacitance VouT = A.C. GND - 8 15 pF
Note: This parameter is periodically sampled and is not 100% tested.
TMM23256P
A.C. CHARACTERISTICS (Ta = 0 ~ 70°C, vCC = 5V l 10%)
sr/LBP-T, PARAMETER T CONDITIONS T MIN. TYP. MAX. l UNIT
ICE CTE pulse width _ 150 - - l ns
tas Address Setup Time - O - l - ns
tar, ' Address Hold Time l - i 30 f l - ns
_. - _ ,_V ,,,,A Wig. __7_. ---- ----f------- i A. - - t _
tacc - _tccess_ee, - - l - - _-assi: as
TOO Output Delay Tune form CE - - - I 70 ns
100 Output THE” Delay - - - 70 ns
tcc cr off Time - 70 v - ns
tcyc Cycle Time tAS =Ons, tr, tt = Ens 230 - T - ns T
. Typcal values are at Ta = 25"C and Vcc = 5V.
A.C. TEST CONDITIONS
0 Output Load .' 1TTL Gate+100pF
q Input Rise and Fall Times (10% ' 90%): 5ns
. Input Pulse Levels : 0.8 ' 2.4V
0 Timing Measurement Reference Levels , Input , 1V and 2CIV
Output , 0.8V and 2.0V
TIMING WAVEFORMS
A0 ~A14 (yt Agiifgs ADDRESS MAY CHANGE X
1 -,','-
I tas tAH tCC
CE tCE F4
L f' k
--- too
OE F v/f-"-"-"-''''"-
tACC poo“)
HtGH - z I XXX r 4% HIGH »2
Do~07 A DATA VALID -———
t1fi1' sie -," .
H------------ - ------- _-¥A -----e
Note (1) too is specified from CE
or ire, whichever occurs first.
TMM23256P
OPERATION INFORMATION
The TMM23256P has two control functions. put buffers, independent of device selection. Assume
The chip enable (CE) controls the operation power ing that E = VIL, the output data is valid at the
and should be used for device selection. The falling outputs after tACC (150ns) from the falling edge of
edge of the E will activate the device and latch the the E.
addresses. The output enable (E) control the out-
The operation modes of the TMM23256P are listed in the following table.
MODE (TE ADDRESS 6Te OUTPUT POWER
Standby H _ - High Impedance Standby
Latch ‘1__ Valid * High Impedance -
Read . L 4FqF L Data Out Active
Output Deselect L . High Impedance Active
Note - , Don't care
WW Address may change after tAH.
APPLICATION INFORMATION
1. POWER SUPPLY DECOUPLING
The operating current 'CC waveforms for TMM
23256P are shown in Fig. l, 2.
The TMM23256P is a clocked device, so the tran-
sient current peaks are produced on the CE transition
and Cl? active level.
The ICC current transients require adequate de-
coupling of Vcc power supply.
2. POWER ON
The TMM23256P requires initialization prior to
normal operation. Two initialization methods are as
follows:
(1) A minimum 100ps time delay is required
after the application of Vcc (+5V) before
proper device operation is achieved. And dur-
ing this period, CE must be at VIH level.
(2) A minimum 100ps time delay is required
after the application of Vcc (5V), and then a
minimum of one initialization cycle must be
performed before proper device operation is
acheived.
Initialization cycle .' An initialization cycle is one
Chip Enable clock cycle from the first down edge of
the CTEtill the next down edge.
ICC (mA)
- 2.0V
ICC (mA)
TMM23256P
1 cycle
1 100 200 300 400 500
Time (ns)
Fig.1 ICC vs. Time M)
1 cycle
0 1 00 200 300 400 500
Time (ns)
Fig.2 ICC vs. Time (2)
TMM23256P
OUTLINE DRAWINGS
Unit:mm
28 27 26 25 24 23 22 21 2019 " 17 16 15
"l-"-"'",'"""""-"---------,
R1.5 I i'
\U Cl Q
- "_------- _ _ - - _-Ci-, E
d p :1
-IuuJuluJLluJiuclulL.rcrurIu
1 2 345 67 tl 91011121314
E 15.24Typ.
I o.5io.15 ll '
2.54io.25 114:0.15 0. MAX. -
"-"'-""1'c''--H----j-- -f-t---'-c----- 11f?_SIA2_, E
Note : Each lead pitch IS 2.54mm. All leads are located wnhm 0.25mm of their true longitudinal position with respect
to No.1 and No.28 leads.
www.ic-phoenix.com
.
