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TMM2064P-10-TMM2064P-15
TOSHIBA MOS MEMORY PRODUCTS
?@SMHIA (iifl(2$) giEliifl(i)y21r [PERIIHUWS
8,192 WORD X tt BIT STATIC RAM TMM2064P-10, TMM2064P-12
N-CHANNEL SILICON GATE MOS
TMM2064P-15
'ttttttttmtv/ttttt
The TMM2064P is a 65, 536 bits high speed and
low power static random access memory organized
as 8,192 words by 8 bits and operates from a single
5V supply. Toshiba's high performance device
technology provides both high speed and low power
features with a maximum access time of 100ns/
120ns/150ns and maximum operating current of
80mA. When CTST is a logical high or C82 is a logical
_ 5% 5m: w
0 Access Time and Current
Parameter Access Operating Standby
Part Time Current Current
Number (Max.) (Max.) (Max.)
TMM2064P-10 100ns 80mA 10mA
TMM2064P-12 120ns 80mA 10mA
TMM2064P-1 5 1 50ns 80mA 10mA
E I/os
SYMBOL NAME
Ao--/u Column Address Inputs
As-Au Row Address Inputs
EST, C32 Chip Select Inputs
W Write Enable Input
l/O, ~I/Oe Data lnput/Output
E Output Enable Input
Vcc Power (5V)
GND Ground
N. C. No Connection
low, the deivce is placed in a low power standby
mode in which maximum standby current is 10mA.
Thus the TMM2064P is most suitable for use in
microcomputer peripheral memory where the tow
power applications are required. The TMM2064P is
fabricated with ion implanted N channel silicon gate
MOS technology for high perfomance and high reli-
ability.
0 Single 5V Power Supply
a Fully Static Operation
0 Power Down Feature : E
0 Output Buffer Control : (f
er Three State Outputs
tt All Inputs and Outputs : Directly ITL Compatible
0 Inputs Protected : All inputs have protection
against static charge.
GENERATOR
PRECHAROE
CIRCUIT
----ov
A6 al MEMORY CELL 00
AT a ARRAY - GND
A8 a at r ..
- 56)- $4 KB
A9 3 '?? I'
9 65536)
A10 t ii
All at a
V01 SENSE AMP
COLUMN DECODER
CONTROL.
AU A1 AZAS "
C '5fts0,s3'r(5Fr,r),T%i,
Tilu' 12064P-10 TNHZBMP-IZ
Ttll FJZOMP-l 5
#155155»: Wt 'i'sS8rth'RFTFf7stfrir"-irra)
")4AtttMttti,1tt,ATtt)ttS /
SYMBOL ITEM RATING UNIT
Vcc Power Supply Voltage -0. 5--7.0 V
VIN, VOUT Input/Output Voltage _O..5.~70 V
Tom Operating Temperature 0-70 'C
Tsrs Storage Temperature -55- 1 50 'C
Tsomsn Soldering Temperature . Time 260 . 10 0590
Po Power Dissipation (Ta=70’C) 1 .0 W
* --3.OV at Pulse width 50ns
'fe"s''i'i'di', 'tS; “R; 55 (Ta= o-- 70 C)
SYMBOL PARAMETER MIN. TYP. MAX. UNIT
VIH Input High Voltage 2.0 - Vcc+1.0 V
v.L Input Low Voltage --0. 5" - 0.8 V
Vcc Supply Voltage 4.5 5.0 5. 5 V
* * -3.0V at Pulse width 50ns
'isiiiTa--= o- 70'C, Vcc= 5. OV+10%)
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
hr. Input Leakage Current VI~=OV~5.5V -10 - 10 PA
VOH Output High Voltage Iour= -I .OmA 2.4 - - V
VOL Output Low Voltage lou1=2.1mA - - 0.4 V
_tiTir--vm or C_Sz =VIL or
ILO Output Leakage Current WE:VIL or OE=VIH. - 1O - 10 szA
Vour=OV~5 5V
CS! =Vcc, CS2 =OV
Isap Peak Power-on Current lour- Om A - - 20 mA
E:\lIH or CS2 =VIL,
Iss Standby Current lour=OmA - 10 mA
. tTgT---ihc, C82=VIH,
Icc Operating Current IOUT= 0m A - 80 mA
?‘f (Ta=26"C, f=1.0 MHz)
SYMBOL PARAMETER CONDITIONS MAX. UNIT
Cm Input Capacitance Vm=OV 5 pF
Cour Output Capacitance Vm=OV 10 pF
* * * Note : This parameter is periodically sampled and is not 100% tested.
- D-18 -
A. c. CHARACTERISTICS (Ta ----0--7tyc, Vcc=5Vi 10%)
Tia Iq20MFI 0. Tl'al2064F1 2
TM F.12064P-l 5
Read Cycle
SYMBOL PARAMETER TMM2064P-10 TMM2064P-12 TMM2064P-1 5 UNIT
MIN. MAX. MIN. MAX. MIN. MAX.
Inc Read Cycle Time 100 - 120 - 150 -
tAcc Address Access Time - 100 - 120 - 1 50
tc01 t5gT Access Time - 100 - 120 - 150
tcoz CS2 Access Time - 100 - 120 - 150
toe E Access Time - 40 - 50 - 60
toH 11put Data Hold Time from Address Change IO - 10 - 1O - ns
tag cs, or CS2 to Output in Low-Z 1O - 1O - 10 -
tcra -c-STor cs; to Output in High-Z - 40 - 40 - 55
totg Tii? to Output in Low-Z 5 - 5 - 5 -
1on BEto Output in High-Z - 35 - 35 - 50
tpu Chip Selection to Power Up Time o - 0 - O -
tPD Chip Deselection to Power Down Time - 50 - 60 - 60
Write Cycle
SYMBOL PARAMETER TMM2064P-1O TMM2064P-12 TMM2064P-1 5 UNIT
MIN. MAX. MIN. MAX. MIN. MAX.
twc Write Cycle Time 100 - 120 - 1 50 -
tcw Chip Selection to End of Write 80 - 100 - 120 -
us Address Set Up Time 10 - 1O - 10 -
twp Write Pulse Width 70 - B5 - 100 - ns
twn Write Recovery Time 0 - O -- O -
tos Data Set Up Time 40 - 50 -- 60 -
ton Data Hold Time 0 - O - O -
twa WE t0 Output in Low-Z 5 - 5 - 5 -
twra 17TE- to Output in High-Z - 30 - 35 - 4o
Input Pulse Levels
VIH=2.2V. VIL=O.6V
Input Rise and Fall Time
Input and Output Reference Levels
Output Load
1 TTL Gate & CL=1OOpF
- D-19 -
Tgl P.12064P-l 0, 'liTalll20MF1 2
TM W120“ Fl 5
TIMING WAVEFORMS
o READ CYCLE (1)
ADDRESSES )(
CS2 (/ I 'C,,, Isl)))))))) lllllllli'
Trirf JTpT,rpi- //////////////////////
m \\\\\\\\\\\\ 5 g/////(/{{///// ///////
o WRITE CYCLE 1 (4) (W? Controlled Write)
tc Lz(5)
cc'f,,"i%W'"
tc LZ(S)
UNKNOWN
OUTPUT DATA VALID
AfF-----
ADDRESSES
W li)):))))))) ,
cs2 f I tar l N
Trg-l s":)(if))):)iliif(i)i))'))):sh tcw 7 /
'wo'o'ow o ' WW 'owvo
ifiiiiiiiiEiz,),iigiiiiEgifr
xla Xl! C _
" IMPEDANCE
- D-20 -
D8 to}!
*DATA ly STABLE
TTIT B'IZIJMP-l 0, TTal20MF1 2
TI‘HWJZOMP-l 5
o WRITE CYCLE 2 (4) (CST Controlled Write)
ADDRESSES -)( (
/ tcw "llllllyllllfllllllllill"
TCLz(5) twazb)
HIGH IMPEDANCE
I tDS tDH
DIN j: DATA IN STABEIQC
tPU tpry
SUPPLY ICC -------------- . - - I[ l
CURRENT ISB
0 WRITE CYCLE 3 (4) (CS2 Controlled Write)
ADDRESSES ( 3L
w 1lllllillli'lllllly l
1_i[llllljlllillllillijrr
CS'd ____2W’ tar \
m ciff"ff"p"fi"'f,h'p"fP, oilliil_lll0lrllljllil,
tcures) twazm)
I HIGH IMPEDANCE
DOUT l
tps tDH
DIN DATA ttt STABLE i)
- D-21 -
TTfl P.12064P-I 0, 'riala20MF.1 2
TTI) m2064P-l ii
Note :
l. WIS High for Read Cycle.
2. Assuming that (TS-i Low transition or cs, High transition occurs coincident with or after VlELow transition, Outputs
remain in a high impedance state.
3. Assuming that a High transition or C82 Low transition occurs coincident with or prior to W High transition,
Outputs remain in a high impedance state.
4. Assuming that O-Eis High for Write Cycle, Outputs are in high impedance state during this period.
5 These parameters are specified as follows and measured by using the load shown in Fig. 1 .
(A) tCLz. toLz, tvsz ............... Output Enable Time
(B) ton, tOHz, twm ..o............ Output Disable Time
- - 5v
Css, OE
WE,csk. L8 kg
(A) Dotrt
0.15v mm
D HIGH IMPEDANCE 0.15v HIGH IMEDANCE cL=50pF
OUT 0.15v
-----y 0.15V
Fig. 1 Output load condition for enable disable time measurement.
OUTLINE DRAWINGS ;
Unit: mm
28272625242522 arm19 18171615
r"tr'"qr"tr"trNr"trnr"tr"Sr"Tr"nr''nr"Sr",
Rl.5 .
L! U '-guaua
1 'dht'"i'Y'd '7 Idhj''rg 11 -dtd'ri
I 37.4 MAX. 15.2t TYP.
at tf'
3 r4mr%rtnr%r+trtnrmrhrH 'f
- I l l l I l l l I n
0.51015 a'
2.541025 lat 0.15 0.2MAX. , l T.A MAX.
NOTES : Each lead pitch is 2 . 54mm. All leads are Iocatsd"vvithin 0.25mm of their true longitudinal position with respect
to No.1 and No.281eads.
Note . Toshiba does not assume any respoostbihty for use of any Circuitry described ; no CII’CUN patent licenses are implied, and Toshiba reserves the right. at any time
without notice. to change said circuitry.
©Aug., 1985 Toshiba Corporation
- D-22 -
www.ic-phoenix.com
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