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TMM2063AP-10-TMM2063AP-12-TMM2063AP-70
100ns ; 80mA; V(cc): -0.5 to +7.0V; 0.8W; 65,536 bits high speed and low power static access memory
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DESCRIPTION
Tlllillllf?063lu'"70, TMM2063AP-lll
TilllllllM6UP-12
The TMM2063AP is a 65,536 bits high speed and low power static random access
memory organized as 8,192 words by 8 bits and operates from a single 5V supply.
Toshiba's high performance device technology provides both high speed and low power
features with a maximum access time of 70ns/lOOns/120ns and maximum operating current
of 80mA.
When Egi is logical high or CS2 is a logical low, the device is placed In
a low power standby mode in which maximum standby current is lOmA.
Thus the TMM2063AP
is most suitable for use in microcomputer peripheral memory where the low power ap-
plications are required, moreover, suitable for use in high density assembly as 0.3
inch width package is use for.
channel silicon gate NOS technology for
The TMM2063AP is fabricated with ion implanted N
high preformance and high reliability.
. Single 5V Power Supply
. Fully Static Operation
. Power Down Feature: Cg1, CS2
. Output Buffer Control: 0E
. Three State Outputs
. All Inputs and Outputs: Directly TTL
FEATURES
. Access Time and Current
arameter Access Operating Standby
Part Time Current Current
Number (Max.) (Max.) (Max.)
Trlrf2063AP-70 70ns 80mA 10mA
THbf2063AP-10 100ns 80mA 10mA
'INN2063AP--12 120ns 80mA lOmA
Compatible
. High Density Assembly Capability:
0.3 inch width package
(28 pins plastic DIP)
PIN CONNECTION
Inc. 1 V...,/ 283VCC
AlZUZ 273V?
A7E3 263082
A654 253A8
A5:5 243Ag
AIC6 233A11
ASC7 2236:
A: t 5 21 2 A10
Alty weorTrl
m: 10 19 3 I/OB
1 '01:); 1831-‘0'7
I Duet 12 17 l 1/06
I 05: L3 163 L/os
JNDE 14 15 , 1/04
PIN NAMES
SYMBOL NAME
AO’VA4 Column Address Inputs
A5sA12 Row Address Inputs
CTI, CS2 Chip Select Inputs
WE Write Enable Input
I/Olq,I/08 Data Input/Output
CE Output Enable Input
VCC Power (+5V)
CND GrOund
N.C. No Connection
- Inputs Protected: All inputs have
protection against
static charge.
BLOCK DIAGRAM
GENERATOR
PRECHARGE
CIRCUIT
MEMORY CELL c CC
--o iD
ARRAY ON
A9
A10 3:3 (65586)
All MC)
SENSE AMP
COLUMN DECODER
CONTROL
CE A0 A1 A2 A3 Al
Ta'll2063liF70, Tra'll2tmliF10
TI, P.12063AP-I 2
MAXUMUM RATINGS
SYMBOL ITEM RATING UNIT
VCC Power Supply Voltage -0.5 $7.0 V
VIN, VOUT Input Output Voltage ~0.55§7.0 V
Topr. Operating Temperature 0'w70 °C
Tstg. Storage Temperature -55 1150 "c
Tsolder Soldering Temperature .Time 260 .10 oC.sec
PD Power Dissipation (Ta=70°C) 0.8 W
*1 -3.0ir at pulse width 50ns
D.C. RECOMMENDED OPERATING CONDITION (Ta=0 m70°C)
SYMBOL PARAMETER MIN. TYP. MAX UNIT
VIH Input High Voltage 2.0 - VCC+1.0 ll
VIL Input Low Voltage -0.5*2 - 0.8 V
VCC Supply Voltage 4.5 5.0 5.5 V
*2 -r,.ov at pulse width SOns
D.C. CHARACTERISTICS (Ta--0ru70''C, VCC=5.OVi107)
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
11L Input Leakage Current VIN=OV’L5-5V -10 - 10 pA
VOH Output High Voltage 1oLt--1.0mA 2.4 - - V
VOL Cutput Low Voltage IOUT=4.0mA - - 0.4 V
E:\rm or csz=vIL or
1L0 Output Leakage Current WF=VIL or (TE---vva, -10 - 10 uA
VOUT=OV l 5. 5v
ISBP Peak Power-on Current Cr1=vcc, CSZ=OV, IOUT=OmA - - 20 mA
ISB Standby Current CSJ=V1H or CSZ=V1L, IOUT=OmA - - 10 mA
ICC Operating Current (FLVIL, C82=VIH, IOUT=OmA - - 80 mA
CAPACITANCE * (Ta=25°C, f=l.0 MHz)
SYMBOL PARAMETER CONDITIONS MAX. UNIT
CIN Input Capacitance VIN=OV 6 F
COUT Output Capacitance VIN=0V 10 p
* Note: This parameter is periodically sampled and is
- D-1O -
not 1002 tested.
'n'lrll2M3liFT0, Tr,1lia20iiupm1
Trg Ia2063llF1 2
A.C. CHARACTERISTICS(Ta=O N7O°C, VCC=5V:lOZ)
READ CYCLE
SYMBOL PARAMETER THN2063AP-70 TNrf2063AP-10 TrOC063AP-12 UNIT
PIN. MAX. MIN. MAX. MIN. MAX.
tRC Read Cycle Time 70 - 100 - 120 -
tACC Address Access Time - 7O - 100 - 120
tc01 m Access Time - 70 - 100 - 120
tcc2 Cg? Access Time - 7O - 100 - 120
tOE (FE Access Time - 35 - 40 - 50
tor; isaizstéazngzld Time from s - w - w -
tCLZ grtggg Enable Time from tm 10 - 10 - 10 _ ns
tCHZ Till Disable Time from EEI - 3O - 40 - 40
tOLZ Output Enable Time from or: 5 - 5 - 5 -
tOHZ Output Disable Time from 5? - 30 - 35 - 35
tptr Chip Selection to Power Up Time 0 - 0 - 0 -
tPD Chip Deselection to Power Down - ho - 50 - 60
WRITE CYCLE
SYMBOL PARAMETER TMM2063AP-70 Tyfyc1063AP-10 TMM2063AP-12 UNIT
MIN. MAX. MIN. MAX. MIN. MAX.
tWC Write Cycle Time 70 - 100 - 120 -
tCW Chip Selection to End of Write 60 - 80 - 100 -
tAS Address Set Up Time 10 - 10 - lO -
twp Write Pulse Width 50 - 7O - 85 -
tWR Write Recovery Time 0 - O - 0 - ns
tDS Data Set Up Time 30 - tro - 50 -
tDH Data Hold Time 0 - 0 - o -
tNLZ Output Enable Time from FT 5 - 5 - 5 -
thZ Output Disable Time frow i?T - 25 - 30 .... 35
A.C. TEST CONDITIONS
Input Pulse Levels
VIH=2.2V, VIL=0.6V
Input Rise and Fall Time
Input and Output Reference Levels
Output Load
1 TTL Cate & CL=100pF
--D-11--
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c."' ‘4,, c_vcrer"i, 1;» w " p ' , _ .
'nuMii3llll'-70, T'M'g206MF10
'rlaf02063llF1 2
[TIMING NAVEFORMS
READ CYCLE (1)
ADDRESSES (
cse m]! :02 si,,i_,,i,r,i,i,i-i-viiir-i"
CT,"1- liiijiiiiy, tCC)1 //{{éZ///////j////////
Fiir.' irir'iirii,,i-,,,.,,,'a'' 1ci,iir/r1-l-
tCLZw’
UNKN OWN
WRITE CYCLE 1 (4)
(WE Controlled Write)
ADDRESSES Vt tu. y
Ir-ii.' ll))))))))), twp /
(3S2 Illijj]jjjiijjjjjj- tcw (/jflilllliillllViir
m l 'k W 'i",l.,ll,l,yil"n
twnz(m tsz(5
Door jifEiEilif "EiEMr, 11di1)Aticii,, (3)
- D-12 -
1 DATA IN STABLE
TTa'll2063l1F70, TTl1lq206MF10
Tm F.12063AP-l 2
WRITE CYCLE 2 (4) (O_l C ooooo lled Write)
$2 UWC', x
TIT- ii)))))),))))))))))))), 'll/il/ii/iii,
S? /////////////o/ tcw Jjll?/lHu%ili
WRITE CYCLE 3 (4) (CS2 c ontro lled Write)
ADDRESSES X TWC IX
TG5 _))))))))):'
"iiiiiiiii/1- twp ol/lil-j/lip-l/l/ll
//// tcw x
m ii'(;i77RriSiii5) x tcw :illi]ili%%V
tCLZ(5) tWHZ(5)
k HE aHIMPEDANCE
DOUT -.-..-t-l-l+
tbs tDH
, DATA IN STABLEl
- D-13 -
Tl'flrl2063lut-N, 1lTa12063llFl0
Tgl itfl206MF1 2
Note: I. WE is High for Read Cycle.
2. Assuming that 5E1 Low transition or CS2 High transition occurs
coincident with or after TIT: Low transition, Outputs remain in a
high impedance state.
3. Assuming that CEl High transition or CS2 Low transition occurs
coincident with or prior to WE High transition, Outputs remain
in a high impedance state.
h. Assuming that GE is High for Write Cycle, Outputs are in high
impedance state during this period.
5. These parameters are specified as follows and measured by using
the load shown in Fig. I.
(A) tCLZ, tou, tWLZ . . . o . . . . . Output Enable Time
(B) tcuz, touz, tWHZ .... ..... Output Disable Time
Chl SV
HIGH IMPEDANCE HIGH IMPEDANCE
L8 k9.
CL=30pF;[
Fig.1 Output load condition for enable disable time measurement.
1.0 k0
- D-14 -
'n'li'J8063l1F70, 1lTl1l'J2tBMFt0
1l'a'J206811Pm?
OUTLINE DRAWINGS
Unit: mm
r-nr-ir-ir-tLC-r-Tr-nr''"-,-'-",.'"",-'-",
L-au-ll-UL-ll-di-JL-Ju-lL-lt,.-., LJI_J '-'''ii"
co. I 305MAX. 4 1621025
1!. l E l
fli7f?i7?7??- L ,
F--. -.-.-- h
a ll 051045 .1
2 141015 '2541025 O.s..1tf
Note: Each lead pitch is 2.54mm. A11 leads are located within 0.25mm
of their true longitudinal position with respect to No.1 and
No.28 leads.
- D-15 -
www.ic-phoenix.com
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