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TMM2018AP-25-TMM2018AP-35-TMM2018AP-45
16,384 bits high speed and low power static random access memory organized as 2,048 words by 8 bits and operates from a single 5V supply
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'nl1i'lla18liF25, Tlllli'll2018llF35, 'nBl2018liF45
DESCRIPTION
The TNN2018AP is a 16,384 bits high speed and low power static random access memory
organized as 2,048 words by 8 bits and operates from a single 5V supply.
Toshiba's high performance device technology provides both high speed and low power
features with a maximum access time of 25ns/35ns/45ns and maximum operating current
of 150mA/135mA/135mA. When CT goes high, the device is deselected and placed in a
low power standby mode In which maximum standby current is 20mA.
Thus the TMM2018AP is most suitable for use In cache memory and high speed storage.
The TMM2018AP is offered in a 24 pin standard plastic package with 0.3 inch width for
high density assembly.
The TMM2018AP is fabricated with ion implanted N channel silicon gate MOS technology
for high performance and high reliability.
FEATURES . Single 5V power supply
. Fast access time . Fully static operation
tACC=25nsz TNN2018AP-25 . All inputs and outputs: Directly TTL compatible
tActy=35ns: TMM2018AP-35 . Power down feature: E§=VIH
tAcc=45ns: TNM2018AP-45 . Output buffer control: JE
. Low power dissipation . Three state outputs
1CC=150mA: ThfM2018AP-25 . Inputs protected: All inputs protection against
ICC=135mAz TNN2018AP-35 static charge.
Icc=135mA: 'nfN2018AP--lr5 . Package: 24 pin standard plastic package, 0.3 inch
ISB=20mA width.
PIN CONNECTION BLOCK DIAGRAM
avE 1 v.., 243Vcc CS
AGE 2 233A?! At
A5C 3 223A9 A5 5 OVCC
A4E 4 f'"N 21DWE Ct
ASE 5 a 20:55 A6 E31 MEMORY ------ot1tlD
A2 6 H 193A10 2; m CELL ARRAY
A1 T > 1836:? A9 t (128716x8)
AOCa A 173D©8 tk
o A A10
1/01: 9 C 1631/07
1/02E10 15 Cl 1/06
1/03Ci11 1431/05 1/01 f
mm 12 w 1/04 1/02 ih'dhr"'
:CEZ COLUMN
PIN NAMES DECODEH
A0sA10 Address Inputs I/be
1/01s1/08 Data Input/Output 1:2;
trs Chip Select Input AO A1 A2 A3
WE Write Enable Input
GE Output Enable Input
Vcc Power (+5V) 'Er.
GND Ground BE
Wymwmmgwwmwwmwnwmwmmmmwmmwwmfiwmfl: CA." re'y: mewflYWWMS m hier! te, "e'pr.'"
mfimmfié’ _'_c,itt)ityiityrtiiiiy4t' ti'),',,,' _,-,,,,,:',,,"-"-'):
liar-tii/tvi-iii-s;
MAXIMUM RATINGS
SYMBOL ITEM RATING UNIT
VCC Power Supply Voltage -3.5n,7.0 ll
VIN Input Voltage -3.5 'u7.0 ll
VI/O Input/Output Voltage -3.5'b7.0 V
Topr Operating Temperature Oeu70 "c
Tstg Storage Temperature -55s150 "c
Tsolder Soldering Temperature °Time 260 ~10 ''Cosec
PD Power Dissipézion 0.9 w
TOUT D.C. Output Current 20 mA
D.C. RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER MIN. TYP. MAX. UNIT
VIH Input High Voltage 2.0 - VCC+1-0
VIL Input Low Jiitage" -3.0* - 0.8 ll
Vcc Power Supply Voltaégm 4.5 5.0 5.5
* Pulse Width: lOns, DC: -0.W (MIN.)
D.C. CHARACTERISTICS (Ta=0'»70°C, VCC=5V110%)
SYMBOL PARAMETER CONDITIONS MIN. MAX UNIT
IIL Input Current VIN=0'”VCC - 11.0 pA
Von Output High QSEESgé - Ion=-4.0mA 2.4 -
VOL Output Low Volcaé;*~_m- IOL=8.OmA - 0.4
ILO Output Leakage Current VOUT=O'”VCC~ C§=VIH - 11.0 pA
----- ~25 - 150
ICC Operating Current C§'=VIL -35 - 135 mA
-45 - 135
I33 Standby Current trg-ww - 20 mA
1SBP Peak Power-on Current CT=vcc, Vcc=0s5.:5v - 40
CAPACITANCE* (Ta=25°C, f=lMHz)
SYMBOL PARAMETER CONDITIONS MAX. UNIT
Cir; Input Capacitance VIN=0V 5
COUT Output Capacitance VOUT=0V 10 pF
* Note: This parameter is periodically sampled and is not 100% tested.
A.C. CHARACTERISTICS
'“WflmflfififiWWQWWflmfiw%wmmflmfl%fi@memmwmfiNyfiamfifimwwmfiklaw p
Tix!tattrig,sar, 1ii:zantruaisa, TTJr7aiimrlllFa
(ra--0's70''c, vcc=5v+-10''/.)
Read Cycle
SYMBOL PARAMETER TrfN2018AP-25 TMM2018AP-35 TMM2018AP-45 UNI
MIN. MAX. MIN. MAX. MIN. MAX.
tRC Read Cycle Time 25 - 35 - 45 -
tACC Address Access Time - 25 - 35 - 45
tco Chip Select Access Time - 25 - 35 - 45
tog Output Enable to Output Valid - 15 - 20 - 20
CCLZ Chip Selection to Output in Lov-2 0 - 0 - 0 -
tCHZ 2,1),'-1lese1ection to Output in - 15 - 20 - 20
tOLZ Output Enable to Output in Low-Z 0 - 0 - O -
t0H2 Output Disable to Output in High-Z - 12 - 15 - 15
t0H Output Data Hold Time 5 - 5 - 5 -
tPU Chip Selection to Power Up Time T 0 - - -
tPD g2;: Deselectlon to Power Down - 20 - 30 - 30
Write Cycle
TNN2018AP-25
THN2018AP-35 TNN2018AP-45
SYMBOL PARAMETER UNIT
MIN. MAX. MIN. MAX. MIN. MAX.
ch Write Cycle Time 25 - 35 - 45 -
tCW Chip Selection to End otprite 20 - 30 - 40 -
tAS Address Set Up Time 0 - 0 - 0 -
twp Write Pulse Width 20 - 3O - 35 - ns
tug Write Recovery Time - - -
tsz WE to Output in Low-Z 0 - - -
Cwnz WE to Output in High-Z - 12 - 15 - 15
tps Data Set Op Time 12 - 15 - 20 -
tDH Data Hold Time 0 - 0 - 0 -
A.C. TEST CONDITIONS
Input Pulse Levels 3.0V/0.0V VCC
Input-Rise and Fall Times 5ns moo
2r,La,e, 3:52;: Timing 2.0il/0.8il 1/0 PIN
Output Load See Fig.1 man
20pe 1
Fig.1 OUTPUT LOAD
o,7srti,twtvrts:srssarwrr,Set ~m
mmmmza. TCEEal0il!it!W, tcr),,,'?);)!;),)
TIMING HAVEFORMS
READ CYCLE 1. (rTt=vw, E§=VIL)
,WvgQwfi3%gfigfifimfiWWfifififiwfififiwflafififififlfifiyfibQRWWmflfififi§§gfifi%¥§gggfifiafifi§§imfizd’-
Add -l)yt(
taco tonz
OE LOE
tOLE I OH
DOUT OUTPUT DATA VALID
READ CYCLE 2. (WE=V]H, OE=V]L)
DOUT OUTPUT DATA VALI
SUPPLY
CURHENT
WRITE CYCLE I.
DATA IN STABLE
'vt,'', 'ts . -": p' ' '''ci'Pvet-eri,er'te4tts"trrTrt Wmmmfimwwmmwmmmm ( _",""
" mi, T q: wmawmwmmgfi
Tf'xiiar1rtrlli14Ki, mizmnmss, mmzmmma
WRITE CYCLE 2.
Tig atNr)r)r)))l)W)))"r)) '/7f777/17h7hj,
12)lir'
OE C'''" Lwuz
Lbs Lvu
DIN 2x( DATA IN STABLE :K<
Note: 1. In read cycle 2, all addresses are valid prior to or coincident
with CT; transition low.
2. The operating temperature (Ta) is guaranteed with transverse air
flow exceeding 400 linear feet per minute.
Ti'x,tiiis)tW!?s1?tt'o', vqr0cjiEyleli)if55, jrr1'Ciiiii3s%ilTiai
OUTLINE DRAHINGS
Unit in mm
n C""t_f-1 n C"'T Cir-t r""n r-n r""t cirn
"r'"''-'-'"'"--'"--''-"-).,
30.0MAX 7.621025
2.5MIN 5.0MAX
_ 0.53:0.15 23.541 0.25
-L., 14:015
Note: Each lead pitch is 2.54mm.
All leads are located within 0.25mm of their longitudinal
position with respect to No.1 and No.24 leads.
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