TLV1548QDBRQ1 ,10-Bit 85 kSPS ADC Ser. Out, Pgrmable Pwr/Pwrdn/Conversion Rate, TMS320 DSP/SPI/QPSI Compat., 8 Ch. SGLS172B − JUNE ..
TLV1549CP ,10-Bit 38 kSPS ADC Ser. Out, Inherent S&H Function, Terminal Compat. W/TLC1549, TLC1549xTLV1549C, TLV1549I, TLV1549M10-BIT ANALOG-TO-DIGITAL CONVERTERSWITH SERIAL CONTROLSLAS071C – JANUAR ..
TLV1549ID ,10-Bit 38 kSPS ADC Ser. Out, Inherent S&H Function, Terminal Compat. W/TLC1549, TLC1549xfeaturesdifferential high-impedance reference inputs thatfacilitate ratiometric conversion, scaling ..
TLV1549IP ,10-Bit 38 kSPS ADC Ser. Out, Inherent S&H Function, Terminal Compat. W/TLC1549, TLC1549xTLV1549C, TLV1549I, TLV1549M10-BIT ANALOG-TO-DIGITAL CONVERTERSWITH SERIAL CONTROLSLAS071C – JANUAR ..
TLV1562IDW ,10-Bit, 2 MSPS ADC Quad Ch. (Config.) w/mux, Pgmable Res. vs. Speed/Conversion Mode, Auto ofeatures make this device a flexible general-purpose data converter. The device can beconfigured as ..
TLV1562IPW ,10-Bit, 2 MSPS ADC Quad Ch. (Config.) w/mux, Pgmable Res. vs. Speed/Conversion Mode, Auto oblock diagramAV DV BDVDD DD DDAP/CH1S/HAM/CH2D (0–9)M 4/8/10-BitSerial/Parallel Conv 3-StateAmplifi ..
TMS320VC5420GGU200 ,Digital Signal Processor SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 200-MIP ..
TMS320VC5420GGU200 ,Digital Signal Processor SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 200-MIP ..
TMS320VC5420PGE200 ,Digital Signal ProcessorMaximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . 41Pin Assignments . . . . . . . . . ..
TMS320VC5421GGU200 ,Digital Signal Processor
TMS320VC5421GGU-200 ,Digital Signal Processor
TMS320VC5441PGF ,Digital Signal Processor
TLV1548QDBRG4Q1-TLV1548QDBRQ1
10-Bit 85 kSPS ADC Ser. Out, Pgrmable Pwr/Pwrdn/Conversion Rate, TMS320 DSP/SPI/QPSI Compat., 8 Ch.
10-Bit-Resolution ADC Programmable Power-DownMode ...1 µA Wide Range Single-Supply Operation of
2.7 V dc to 5.5 V dc Analog Input Range of 0 V to VCC�
Built-in Analog Multiplexer with 8 Analog
Input Channels TMS320 DSP and Microprocessor SPI and
QSPI Compatible Serial Interfaces End-of-Conversion (EOC) Flag Inherent Sample-and-Hold Function Built-In Self-Test Modes
descriptionThe TLV1548 is a CMOS 10-bit switched-capacitor successive-approximation (SAR) analog-to-digital (A/D)
converter. The device has a chip select (CS), input-output clock (I/O CLK), data input (DATA IN) and serial data
output (DATA OUT) that provides a direct 4-wire synchronous serial peripheral interface (SPI, QSPI) port
of a host microprocessor. When interfacing with a TMS320 DSP , an additional frame sync signal (FS) indicates
the start of a serial data frame. The device allows high-speed data transfers from the host. The INV CLK input
provides further timing flexibility for the serial interface.
In addition to a high-speed converter and versatile control capability, the device has an on-chip 11-channel
multiplexer that can select any one of eight analog inputs or any one of three internal self-test voltages. The
sample-and-hold function is automatic except for the extended sampling cycle, where the sampling cycle is
started by the falling edge of asynchronous CSTART. At the end of the A/D conversion, the end-of-conversion
(EOC) output goes high to indicate that the conversion is complete. The TLV1548 is designed to operate with
a wide range of supply voltages with very low power consumption. The power saving feature is further enhanced
with a software-programmed power-down mode and conversion rate. The converter incorporated in the device
features differential high-impedance reference inputs that facilitate ratiometric conversion, scaling, and
isolation of analog circuitry from logic and supply noise. A switched-capacitor design allows low-error
conversion over the full operating temperature range.
The TLV1548 has eight analog input channels. The TLV1548Q is characterized for operation over the full
automotive temperature range of −40°C to 125°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
CSTART
GNDCC
EOC
I/O CLK
DATA IN
DATA OUT
REF+
REF−
INV CLK
DB PACKAGE
(TOP VIEW)
