TLE7230G ,Smart Octal Low-Side SwitchFeatures Product Summary ♦ Full Protection Supply voltage V 4.5 – 5 ..
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TLE7230G-TLE7230R
Smart Octal Low-Side Switch
Target Datasheet TLE7230 R/G Smart Octal Low-Side Switch Features Product Summary ♦ Full Protection Overload
Overtemperature
Overvoltage Low Quiescent Current< 10µA 16 bit SPI (for Daisychain) Direct Parallel Control of Four Channels PWM input (demux) Parallel Inputs High or Low Active Programmable Programmable functions
Boollean operation Overload behavior
Overtemperature behavior
Switching time General Fault Flag Digital Ports Compatible to 5V and 3,3 V Micro Controllers
Electostatic Discharge (ESD) Protection Full reverse current capability without latchup or loss of function
General description Detailed Block Diagram Octal Low-Side Switch in
Smart Power Technology
(SPT) with a
Serial Peripheral
Interface (SPI) and eight open drain DMOS output stages. The TLE 7230 R/G is pro-
tected by embedded protec-tion functions and designed for
automotive applications.
SCLK
GND
IN1
IN2
IN3
IN4
OUT8
VDO
Target Datasheet TLE7230 R/G Power SO 36 package
Pin Description Pin Configuration (Top view) Heat Slug internally connected to ground pins
Target Datasheet TLE7230 R/G SO 24 package (thermal enhanced)
Pin Description Pin Configuration (Top view) Heat Slug internally connected to ground pins
Target Datasheet TLE7230 R/G Maximum Ratings for Tj = – 40°C to 150°C Target Datasheet TLE7230 R/G Electrical Characteristics
1. Power Supply, Reset Supply Voltage1 V
2. Outputs
3. Digital Inputs Input Low Voltage
Input Voltage Hysteresis
Input Pull Down Current (SI, SCLK)
4. Digital Outputs (SO, Fault) Output Tri-state Leakage Current CS = H, 0 ≤ VSO ≤ VS
Target Datasheet TLE7230 R/G Electrical Characteristics cont.
5. Diagnostic Functions
6. SPI-Timing (for VVDO = 4.5V to 5.5V) Serial Clock Frequency (depending on SO load)
Serial Clock Period (1/fclk)
Enable Lag Time (falling edge of CLK to rising edge ofCS)
Disable Time @ CL = 50 pF2
Transfer Delay Time3
(CS high time between two accesses)
2 This parameter is not subject to production test
Target Datasheet TLE7230 R/G Functional Description The TLE 7230 R/G is an octal-low-side power switch which provides a serial peripheral interface (SPI)
to control the 8 power DMOS switches, as well as diagnostic feedback. The power transistors are pro-tected4) against overload (current limitation), overtemperature and against overvoltage by an active
zener clamp. The diagnostic logic recognizes a fault condition which can be read out via the serial di-
agnostic output (SO).
Output Stage Control: Parallel Control or SPI Control The Output stages can be controlled by parallel Inputs or by SPI command. The IC can be pro-
grammed (by SPI) to switch the outputs according to the corresponding SPI command bit or to a com-bination of SPI bit and parallel input signal. The logic combination of parallel and serial signal is pro-
grammable by SPI (Boolean operation) to logic "AND" or "OR" The respective SPI databits are high active, the parallel Inputs are high or low active according to the PRG pin (see pin description).
Boolean operation: The logic combination of the parallel and the serial input signal can be configured by an
SPI command for each of the 8 channels
individually. Logic "AND" or logic "OR" is possible.
Mappable parallel input (IN 4): By SPI Command the parallel input 4 (IN4 or IN) can be defined as parallel input for one or more power outputs. Depending on the Input Map Register this input can be used to controll one up to eight of the
parallel outputs. Default operation: IN4 / IN is the parallel input for channel 4.
Switching speed / Slew rate: The switching speed / slew rate of all 8 channels can be configured by SPI for slow or fast switching
speed (1:5) for each channel individually.
Overtemperature Behavior: Each channel has an overtemperature sensor and is individually protected against overtemperature.
As soon as overtemperature occurs the channel is immediately turned off and the overtmperature in-formation is reported by diagnosis. In this case there are two different behaviours of the affected chan-
nel that can be selected by SPI (for all channels individually).
Autorestart: as long as the input signal of the channel remains on (e.g. parallel input high) the channel turns automatically on again after cooling down.
Target Datasheet TLE7230 R/G Latching: After overtemperature shutdown the channel stays off until the overtemperature latch is re-set by a new LÆH transition of the input signal. Note: The overtemperature sensors of the output channels are only active if the channel is turned on.
Low Quiescent current mode (Sleep mode) : By applying ay low signal at the Reset Pin the device can be set to Sleep mode. In this mode all out-
puts are turned off, the diagnosis and biasing is disabled, the diagnosis and the on/off register are re-seted and the current consumption drastically reduced (<10µA). After a reset the outputs are Off, ex-
cept the outputs are controlled by parallel inputs.
Overload Protection: The IC can be programmed to react in different ways to overload.
Only Current limit: The IC actively limits the current to the specified current lmit value. If the current limitation is active for longer than the fault filtering time this fault is reported and stored in the Fault reg-
ister. The channel is not shutdown.
Current limit + shutdown: The IC actively limits the current to the specified current lmit value. If this cur-rent limit is active for more than the specified Overload switch off delay time the affected channel is
turned off and the fault is reported and stored in the fault register. To turn on the channel again this overload latch has to be reset before with an LÆ H transition of the input signal (parallel /SPI depend-
ing on the programmed operation).
Pin description:
OUTPUT 1 to 8 – Drain pins of the 8 channels. Output pins and connected to the load.
GND – Ground pins.
IN 1 to 3 – Parallel Input Pins of the channels 1 to 3
IN 4 / IN – Mappable parallel Input Pin. Can be assigned to different outputs by SPI command. Default Output is OUT4
PRG - Program pin. PRG = High (VS): Parallel inputs 1 to 4 are high active PRG = Low (GND): Parallel inputs 1 to 4 are low active.
If the parallel input pins are not connected (independent of high or low activity) it is guaranteed
that the channels 1 to 4 are switched OFF. PRG pin itself is internally pulled up when it is not connected.
Reset - If the reset pin is in a logic low state, it clears the SPI shift register and switches all outputs OFF. An internal pull-up structure is provided on chip.
Fault - There is a general fault pin (open drain) which shows a high to low transition as soon as an error occurs for any one of the eight channels. This fault indication can be used to gen-
erate a µC interrupt. Therefore a ‘diagnosis’ interrupt routine need only be called after this fault
indication. This saves processor time compared to a cyclic reading of the SO information.
VDO – Supply pin of the push-pull digital output drivers. This pin can be used to vary the high-state output voltage of the SO pin.
Vs – Logic supply pin. This pin is used to supply the integrated circuitry.
