TLE7209-2R Fast Delivery |IC PHOENIX CO.,LIMITED

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TLE7209-2R
Smart Motorbridges + Driver ICs
A H-Bridge for DC-Motor Applications TLE7209-2R
Preliminary Datasheet
1Overview
1.1FeaturesOperating supply voltage 5V to 28V
Typical RDSon=150mΩ for each output transistor
(at 25°C)Continuous DC load current 3.5 A (TC < 100 °C)Output current limitation at typ. 6.6 A±1.1AShort circuit shut-down for output currents over 8ALogic- inputs TTL/CMOS-compatibleOutput switching frequency up to 30kHzRise and fall times optimized for 0.5-2 kHzOver-temperature protectionShort circuit protectionUndervoltage disable functionDiagnostic by SPI or Status-Flag (configurable)Enable and Disable inputP-DSO-20-12 power package
Functional Description
The TLE7209-2R is an intelligent full H-Bridge, designed for the control of DC and
stepper motors in safety critical applications and under extreme environmental
conditions.
The H-Bridge is protected against over-temperature and short circuits and has an under
voltage lockout for all the supply voltages “VS” (main DC power supply). All malfunctions
cause the output stages to go tristate.
The device is configurable by the DMS pin. When grounded, the device gives diagnostic
information via a simple error flag. When supplied with VCC=5V, the device works in
SPI mode. In this mode, detailed failure diagnosis is available via the serial interface.
1.2Pin Configuration
Figure1Pinout TLE7209-2R
Table1Pin Definitions and Functions
Table1Pin Definitions and Functions (cont’d)
1.3Block Diagram
Figure2Block Diagram TLE7209-2R
Circuit Description2.1Control Inputs
The bridge is controlled by the Inputs IN1, IN2, DIS and EN as shown in Table2. The
outputs OUT1 and OUT2 are set to High or Low by the parallel inputs IN1 and IN2,
respectively. In addition, the outputs can be disabled (set to tristate) by the Disable and
Enable inputs DIS and EN.
Inputs IN1, IN2 and DIS have an internal pull-up. Input EN has an internal pull-down.
Table2Functional Truth TableIf Mode “Status-Flag” is selected (see Chapter2.4)If Mode “SPI-Diagnosis” is selected (see Chapter2.4)
2.2Power Stages
Four n-channel power-DMOS transistors build up the output H-bridge. Integrated circuits
protect the outputs against over current and over-temperature if there is a short-circuit to
ground, to the supply voltage or across the load. Positive and negative voltage spikes,
which occur when switching inductive loads, are limited by integrated freewheeling
diodes. To drive the gates of the high-side DMOS, an internal charge pump is integrated
to generate a voltage higher than the supply voltage.
2.2.1Chopper Current Limitation
To limit the output current at low power loss, a chopper current limitation is integrated as
shown in Figure3. The current is measured by sense cells integrated in the low-side
switches. As soon the current limit IL is reached, all switches are switched off for a fixed
time ta.
Figure3Chopper current limitation
2.2.2Temperature-depending Current Reduction
For 165°C4
Figure4Temperature dependent current reduction
2.3Protection
The TLE7209-2R is protected against short circuits, overload and invalid supply voltage
by the following measures:
2.3.1Short circuit to Ground
The high-side switches are protected against a short of the output to ground by an over
current shut-down. If a high-side switch is turned on and the current rises above the short
circuit detection current IOUK all output transistors are turned off after a typical filter time
of 2 µs, and the error bit “Short Circuit to Ground on output 1 (2)”, SCG1 (SCG2) is stored
in the internal status register.
2.3.2Short circuit to VS
Due to the chopper current regulation, the low-side switches are already protected
against a short to the supply voltage. To be able to distinguish a short circuit from normal
current limit operation, the current limitation is deactivated for the blanking time tb after
the current has exceeded the current limit threshold IL. If the short circuit detection
current IOUK is reached within this blanking time, a short circuit is detected (see
Figure5). All output transistors are turned OFF and the according error bit “Short Circuit
to Battery on output 1 (2)”, SCB1 (SCB2) is set.
Figure5Short to Vs detection. Left: normal operation. Right: short circuit is
detected
2.3.3Short circuit across the load
If short circuit messages from high- and low-side switch occur simultaneously within a
delay time of typically 2µs, the error bit “Short Circuit Over Load”, SCOL is set.
2.3.4Over-Temperature
In case of high DC-currents, insufficient cooling or high ambient temperature, the chip
temperature may rise above the thermal shut-down temperature TSD. In that case, all
output transistors are shut-down and the error-bit “Over-Temperature”, OT is set.
2.3.5Under-Voltage shut-down
If the supply-voltage at the VS pins falls below the under-voltage detection threshold, the
outputs are set to tristate and the error-bit “Under-Voltage at VS“ is set.
2.4Diagnosis
The Diagnosis-Mode can be selected between SPI-Diagnosis and Status-Flag
Diagnosis. The choice of the Diagnosis-Mode is selected by the voltage-level on Pin12
(DMS Diagnosis Mode Selection):DMS = GND, Status-Flag Mode
DMS = VCC, SPI-Diagnosis Mode
For the connection of Pins SDI, SDO, CSN and SCK/SF see Figure14 and Figure15.
2.4.1Status-Flag (SF) Mode (DMS = GND)
2.4.1.1SF output
In SF-mode, pin 2 is used as an open-drain output status-flag. The pin has to be pulled
to the logic supply voltage with a pull-up resistor, 47kOhm recommended.
In case of any failure that leads to a shut-down of the outputs, the status-flag is set (e.g.
SF pin pulled to low). These failures are:Under Voltage on VSShort circuit of OUT1 or OUT2 against VS or GNDShort circuit between OUT1 and OUT2Over-currentOver-temperature
SF is also pulled low when the outputs are disabled by EN or DIS.
2.4.1.2Fault storage and resetIn case of under-Voltage, the failure is not latched. As soon as VS falls below the
under-Voltage detection threshold, the output stage switches in tristate and the status-
flag is set from high level to low-level. If the voltage has risen above the specified value
again, the output stage switches on again and the status-flag is reset to high-level.
The Under Voltage failure is shown at the SF pin for VS in the voltage range below the
detection threshold (typical 4.2V) down to 2.5V.In the SF-mode, all internal circuitry is supplied by the voltage on VS. For that reason,
a loss of VS supply voltage leads to a reset of all stored information (Power-ON-
Reset). This Power-ON-Reset occurs as soon as under-Voltage is detected on VS In case of short circuit, over-current or over-temperature, the fault will be stored.
The output stage remains in tristate and the status-flag at low-level until the error is
reset by one of the following conditions: H -> L on DIS, L -> H on EN or Power-ON
Reset.
2.4.2SPI-Mode (DMS = 5V)
2.4.2.1SPI-Interface
The serial SPI interface establishes a communication link between TLE7209-2R and the
systems microcontroller. The TLE7209-2R always operates in slave mode whereas the
controller provides the master function. The maximum baud rate is 2 MBaud (200pF on
SDO).
By applying an active slave select signal at CSN the TLE7209-2R is selected by the SPI
master. SDI is the data input (Slave In), SDO the data output (Slave Out). Via SCK
(Serial Clock Input) the SPI clock is provided by the master. In case of inactive slave
select signal (High) the data output SDO goes into tristate.
The first two bits of an instruction may be used to establish an extended device-
addressing. This gives the opportunity to operate up to 4 Slave-devices sharing one
common CSN signal from the Master-Unit (see Figure7)
Figure6SPI block-diagram
2.4.2.2Characteristics of the SPI InterfaceWhen DMS is > 3.5V, the SPI is active, independently of the state of EN or DIS. During
active reset conditions (DMS < 3.5V) the SPI is driven into its default state. When reset
becomes inactive, the state machine enters into a wait-state for the next instruction. If the slave select signal at CSN is inactive (high), the state machine is forced to enter
the wait-state, i.e. the state machine waits for the following instruction. During active (low) state of the select signal CSN the falling edge of the serial clock
signal SCK will be used to latch the input data at SDI. Output data at SDO are driven
with the rising edge of SCK (see timing diagram Figure13)Chip-address:
In order to establish the option of extended addressing the uppermost two bits of the
instruction-byte (i.e the first two SDI-bits of a Frame) are reserved to send a chip-
address. To avoid a bus conflict the output SDO must stay high impedance during the
addressing phase of a frame (i.e. until the address-bits are recognized as valid chip-
address). If the chip-address does not match, the data at SDI will be ignored and SDO
remains high impedance for the complete frame. See also Figure7Verification byte:
Simultaneously to the receipt of an SPI instruction TLE7209-2R transmits a
verification byte via the output SDO to the controller. Refer to Figure8. This byte
indicates normal or abnormal operation of the SPI. It contains an initial bit pattern and
Because only read access is used in the TLE7209-2R, the SDI data-bits (2nd byte)are not usedInvalid instruction/access:
An instruction is invalid if an unused instruction code is detected (see tables with SPI
instructions). In case an unused instruction code occurred, the data byte “ffhex” (no
error) will be transmitted after having sent the verification byte. This transmission
takes place within the same SPI-frame that contained the unused instruction byte. In
addition any transmission is invalid if the number of SPI clock pulses (falling edge)
counted during active CSN differs from exactly 16 clock pulses. If an invalid instruction
is detected, bit TRANS_F in the following verification byte (next SPI transmission) is
set to HIGH. The TRANS_F bit must not be cleared before it has been sent to the
micro controller.Transfer error bit TRANS_F:
The bit TRANS_F indicates an error during the previous transfer. An error is
considered to have occurred when an invalid command was sent, the number of SPI
clock pulses (falling edge) counted during active CSN was less than or greater than
16 clock pulses, or SPI clock (SCK) was logical high during falling edge of CSN.
Figure7Bus-arbitration by chip-address
2.4.2.3SPI-Communication
The 16 input bits consist of the SPI-instruction byte and a second, unused byte. The 16
output bits consist of the verification-byte and the data-byte (see also Figure8). The
definition of these bytes is given in the subsequent sections.
Figure8SPI communication
2.4.2.4SPI instruction
The uppermost 2 bit of the instruction byte contain the chip-address. The chip-address
of the TLE7209-2R is 00. During read-access, the output data according to the register
requested in the instruction byte are applied to SDO within the same SPI frame. That
means, the output data corresponding to an instruction byte sent during one SPI frame
are transmitted to SDO during the same SPI frame.
Table3SPI Instruction Format
MSB
Table4SPI instruction Description
2.4.2.5Verification Byte
The default value after power-up at DMS of the TRANS_F bit is L (previous transfer valid)
Table5SPI Instruction-Bytes Encoding
Table6Verification Byte Format
MSB
Table7Verification Byte Description
2.4.2.6Data-byte: Diagnostics/Encoding of Failures
(Register DIA_REG, SPI Instruction RD_DIA)
Table8DIA_REG Format
MSB
Table9DIA_REG Description
Default value after reset is FFhex. Access by controller is read only
Failure Encoding in case of multiple faults
If multiple faults are stored in the failure register, the faults that are encoded in the DIAxx
bits can not be displayed simultaneously due to the encoding scheme that is used. In this
case, errors are encoded according to the following priority list. Priority 1: Under Voltage (please note that after removal of Under Voltage, the original
error will be restored, see below)Priority 2: Short circuit across the loadPriority 3: all other short circuitsPriority 4: open load
If a failure of higher priority is detected, the failures of lower priority are no longer visible
in the encoded SPI message.
Fault storage and reset of the Diagnosis Register DIA_REG
Register DIA_REG is reset upon the following conditions: With the rising edge of the CSN-Signal after the SPI-instruction RD_DIA. This reset
only takes place if the correct number of 16 SCK pulses has been counted.When the voltage on DMS exceeds the threshold for detecting SPI-Mode (after Under
Voltage condition). Under Voltage on Vs (typ. < 5,0V) sets Bit 0.... Bit 3 of DIA_REG
to 0000. If Vs rises above the Under Voltage level, Bits of DIA_REG are restored
(when DMS > 3.5V).A rising edge on EN or a falling edge on DIS re-activates the output power-stages, and
resets the DIA_REG register.
Table10Encoding of the Diagnostic Bits of OUT1 and OUT2

Partno	Mfg	Dc	Qty	Available	Descript
TLE7209-2R \|TLE72092R	INF	N/a	1	avai	Smart Motorbridges + Driver ICs