TLE6244X ,Smart Low Side SwitchesFeaturesThe following types of error can be detected:Short-circuit to U (SCB)BattShort-circuit to g ..
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TLE6244X
Smart Low Side Switches
18 Channel Smart Lowside Switch
ASSP for Powertrain
FeaturesShort Circuit ProtectionOvertemperature ProtectionOvervoltage Protection16 bit Serial Data Input and Diagnostic Output
(2 bit/chan. acc. SPI Protocol)Direct Parallel Control of 16 channels for PWM
ApplicationsLow Quiescent CurrentCompatible with 3.3V MicrocontrollersElectrostatic discharge (ESD) Protection
General description18-fold Low-Side Switch (0.35 Ω to 1 Ω) in Smart Power Technology (SPT) with a Serial Pe-
ripheral Interface (SPI) and 18 open drain DMOS output stages. The TLE6244X is protected
by embedded protection functions and designed for automotive and industrial applications.
The output stages are controlled via SPI Interface. Additionally 16 of the 18 channels can be
controlled direct in parallel for PWM applications. Therefore the TLE6244X is particularly
suitable for engine management and powertrain systems.
1. Description
1.1 Short DescriptionThis circuit is available in MQFP64 package or as chip.
1.1.1 Features of the Power Stages*) only serial control possible (via SPI)
Parallel connection of power stages is possible (see 1.13)
Internal short-circuit protection
Phase relation: non-inverting (exception: IN8->OUT8 is inverting)
1.1.2 Diagnostic FeaturesThe following types of error can be detected:
Short-circuit to UBatt (SCB)
Short-circuit to ground (SCG)
Open load (OL)
Overtemperature (OT)
Individual detection for each output.
Serial transmission of the error code via SPI.
1.1.3 VDD-MonitoringLow signal at pin ABE and shut-off of the power stages if VDD is out of the permitted range.
Exception: If OUT8 is controlled by IN8, OUT8 will only be switched off by the overvoltage
detection and not by undervoltage detection.
The state of VDD can be read out via SPI.
1.1.4 µsec-busAlternatively to the parallel and SPI control of the power stages, a high speed serial bus inter-
face can be configured as control of the power stages OUT1...OUT7 and OUT9...OUT16.
1.1.5 Power Stage OUT8OUT8 can be controlled by SPI or by the pin IN8 only. When controlled by IN8 this power stage
is functional if the voltage at the pin VDD is above 3,5V. OUT8 will not be reset by RST. In
SPI mode the power stage is fully supervised by the VDD-monitor.
1.2 Block DiagramUBatt
RSTSO
SCK
OUT1
OUT3
OUT4
OUT5
OUT6
OUT2
OUT7
OUT8
OUT9
OUT10
OUT11
OUT12
OUT13
OUT14
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
IN11
IN12
IN13
IN14OUT15
OUT16OUT18
IN16
IN9
IN10
GND1...8
ABE
GND_ABE
VDDOUT17
IN15
OUT1... OUT66 non-inverting low side power switches for nominal currents up to 2.2A. Control is possible by
input pins, by the µsec-bus or via SPI. For TJ = 25°C the on-resistance of the power switches is
below 400mΩ.
An integrated zener diode limits the output voltage to 70V typically.
A protection for inverse current is implemented for OUT1... OUT4 for use as stepper-motor con-
trol.
OUT9... OUT146 non-inverting low side power switches for nominal currents up to 2.2A. Control is possible by
input pins, by the µsec-bus or via SPI. For TJ = 25°C the on-resistance of the power switches is
below 380mΩ.
An integrated zener diode limits the output voltage to 45V typically.
OUT15, OUT162 non-inverting low side power switches for nominal currents up to 3.0A. Control is possible by
input pins, by the µsec-bus or via SPI. For TJ = 25°C the on-resistance of the power switches is
below 280mΩ.
An integrated zener diode limits the output voltage to 45V typically.
OUT7, OUT8, OUT17, OUT184 low side power switches for nominal currents up to 1100mA. Stage 7 is non-inverting, Stage 8
is inverting (IN8 = ‘1’ => OUT8 is active). For the output OUT7 control is possible by the input pin,
by the µsec-bus or via SPI, OUT8 is controlled by the input pin IN8 or via SPI, for the outputs
OUT17 and OUT18 control is only possible via SPI. For TJ = 25°C the on-resistance of the power
switches is below 780mΩ.
An integrated zener diode limits the output voltage to 45V typically.
In order to increase the switching current or to reduce the power dissipation parallel connection
of power stages is possible (for additional information see 1.13).
The power stages are short-circuit proof:
Power stages OUT1...OUT8, OUT11.14: In case of overload (SCB) they will be turned off after a
given delay time. During this delay time the output current is limited by an internal current control
loop.
Power stages OUT9, OUT10, OUT15...OUT18:
In case of SCB these power stages can be configured for a shut-down mode or for static current
limitation. In the shut down mode while SCB they will behave like OUT1..8 or OUT11..14.
In case of static current limitation and SCB the current is limited and the corresponding bit com-
bination is set (early warning) after a given delay time. They will not be turned off. If this condition
leads to an overtemperature condition, the output will be set into a low duty cycle PWM (selective
thermal shut- down with restart) to prevent critical chip temperature.
There are 3 possibilities to turn the power stages on again:
- turn the power stage off and on, either via serial control (SPI) or via parallel control (input pin,
except outputs OUT17 and OUT18) or by the µsec-bus (except OUT8, OUT17,OUT18)
- applying a reset signal.
- sending the instruction “del_dia” by the SPI-interface
The VDD-monitoring locks all power stages, except OUT8 for access by the IN8 input. OUT8 is
locked by an internal threshold of 3,5V maximum when controlled by IN8. Otherwise OUT8 is
All low side switches are equipped with fault diagnostic functions:
- short-circuit to UBatt:(SCB) can be detected if switches are turned on
- short-circuit to ground:(SCG) can be detected if switches are turned off
- open load:(OL) can be detected if switches are turned off
- overtemperature:(OT) will only be detected if switches are turned on
The fault conditions SCB, SCG, OL and OT will not be stored until an integrated filtering time is
expired (please note for PWM application). If, at one output, several errors occur in a sequence,
always the last detected error will be stored (with filtering time). All fault conditions are encoded
in two bits per switch and are stored in the corresponding SPI registers. Additionally there are
two central diagnostic bits: one specially for OT and one for fault occurrence at any output.
The registers can be read out via SPI. After each read out cycle the registers have to be cleared
by the DEL_DIA command.
1.3.1 Power Stage OUT8 (Condensed Description)1.3.1.1 Control of OUT8 and VDD-Monitoring
OUT8 can be controlled by SPI or by the pin IN8 only, control by µs-bus is not possible. When
controlled by IN8 this power stage is functional if the voltage at the pin VDD is above 3,5V. In
SPI mode the power stage is fully supervised by the VDD-monitor.
If OUT8 is controlled by IN8, OUT8 will only be switched off by the overvoltage detection and
not by undervoltage detection.
1.3.1.2 Phase Relation IN8 - OUT8
The phase relation IN8 -> OUT8 is inverting.
OUT8 is active if IN8 is set to logic '1' (high level, see 3.4.2 ) in case of parallel access.
On executing the read instruction on RD_INP1/2 the inverted status of IN8 is read back.
1.3.1.3 Reset / Power Stage Diagnostics
If OUT8 is controlled by IN8, OUT8 will not be reseted by RST.
After reset parallel control (by IN8) is active for OUT8.
If UVDD < 4.5V errors are not stored because of the active RST of the external Regulator. Nev-
ertheless
OUT8 is protected against overload.
1.3.1.4 Input Current
The control input IN8 has an internal pull-down current source. Thus the input currents I IN8
are positive (flow into the pin).
1.3.1.5 On Resistance
For OUT8 and 3.5V < UVDD < 4.5V R on increases (see 3.8.5).
1.3.1.6 Parallel Connection of Power Stages
Parallel connection of power stages with OUT8 and parallel control is prohibited (inverting
input IN8). Control via SPI is possible. See 1.13.
Function Pin Pin Number
Input 1IN17
Input 2IN246
Input 3IN310
Input 4IN443
Input 5IN56
Input 6 or FDAIN663
Input 7 or SSYIN761
Input 8IN822
Input 9IN920
Input 10IN1033
Input 11IN115
Input 12IN1248
Input 13IN1313
Input 14IN1440
Input 15IN151
Input 16 or FCLIN1662
Output 1OUT18
Output 2OUT245
Output 3OUT39
Output 4OUT444
Output 5_1OUT5_116
Output 5_2OUT5_217
Output 6_1OUT6_137
Output 6_2OUT6_236
Output 7OUT760
Output 8OUT857
Output 9_1OUT9_118
Output 9_2OUT9_219
Output 10_1OUT10_135
Output 10_2OUT10_234
Output 11OUT114
Output 12OUT1249
Output 13_1OUT13_114
Output 13_2OUT13_215
Output 14_1OUT14_139
Output 14_2OUT14_238
Output 15_1OUT15_12
Output 15_2OUT15_23
Output 16_1OUT16_151
Output 16_2OUT16_250
Output 17OUT1725
Output 18OUT1828
(Note: OUTxy_1 and OUTxy_2 have to be connected externally!)Slave SelectSS56
Serial OutputSO53
Serial InputSI55
SPI ClockSCK54
Supply Voltage VDDVDD47
Supply Voltage UBattUbatt23
GND1GND126
GND2GND227
GND3GND358
GND4GND459
GND5GND511
GND6GND612
GND7GND742
GND8GND841
Sense Ground VDD-MonitoringGND_ABE29
In-/Output VDD-MonitoringABE30
Reset (low active)RST31
not connectednc21, 24, 32, 52, 64
OUT6_1
OUT14_2
OUT10_1
OUT6_2
OUT10_2
OUT14_1
OUT16_2
OUT16_1
HiQUAD64
IN1 to IN16Control inputs of the power stages
Internal pull-up current sources (exception: IN8 with pull-down current
source)
FCLClock for the µsec-bus (pin shared with IN16)
FDAData for the µsec-bus (pin shared with IN6)
SSYStrobe and Synchronisation for the µsec-bus (pin shared with IN7)
OUT1 to OUT18Outputs of the power switches
Short-circuit proof
Low side switches
Limitation of the output voltage by zener diodes
VDD Supply voltage 5V
UBattSupply voltage UBatt
Pin must not be left open but has to be connected either to UBatt or to VDD
(e.g. in commercial vehicles)
GND1 to GND8Ground pins
Ground pins for the power stages (see 2.4)
Ground reference of all logic signals is GND1/2
RSTReset
Active low
Locks all power switches regardless of their input signals (except OUT8)
Clears the fault registers
Resets the µsec-bus interface registers
ABEIn-/Output VDD-Monitoring
Active low
Output pin for the VDD-Monitoring
Input pin for the shut-off signal coming from the supervisor
GND_ABESense ground VDD-Monitoring
SI, SO, SCK, SSSPI Interface
The serial SPI interface establishes a communication link between TLE6244X and the systems mi-
crocontroller. TLE6244X always operates in slave mode whereas the controller provides the mas-
ter function. The maximum baud rate is 5 MBaud.
The TLE6244X is selected by the SPI master by an active slave select signal at SS and by the first
two bits of the SPI instruction.SI is the data input (Slave In), SO the data output (Slave Out). Via
SCK (Serial Clock Input) the SPI clock is provided by the master.
In case of inactive slave select signal (High) the data output SO goes into tristate.
Block Diagram: SO
SCK
SI
SS
Power Stages 1..16
Power Stages 1..18
Power Stages 1..18
VDD-Monitoring
A SPI communication always starts with a SPI instruction sent from the controller to TLE6244X.
During a write cycle the controller sends the data after the SPI instruction, beginning with the MSB.
During a reading cycle, after having received the SPI instruction, TLE6244X sends the correspond-
ing data to the controller, also starting with the MSB.
SPI Command/Format:
Characteristics of the SPI Interface:If the slave select signal at SS is High, the SPI-logic is set on default condition, i.e. it expects
an instruction. If the 5V-reset (RST) is active, the SPI output SO is switched into tristate.
The VDD monitoring (ABE) has no influence on the SPI interface.
3) Verification byte:
Simultaneously to the receipt of an SPI instruction TLE6244X transmits a verification
byte via the output SO to the controller. This byte indicates regular or irregular operation of
the SPI. It contains an initial bit pattern and a flag indicating an invalid instruction of the previous
access.
4) On a read access the databits at the SPI input SI are rejected. On a writing access or after
the DEL_DIA instruction the TLE6244XTLE6244X sets the SPI output SO to low after sending
the verification byte. If more than 16 bits are received the rest of the frame is rejected.
5) Invalid instruction/access:
An instruction is invalid, if one of the following conditions is fulfilled:
- an unused instruction code is detected (see tables with SPI instructions)
- in case the previous transmission is not completed in terms of internal data processing
- number of SPI clock pulses counted during active SS differs from exactly 16 clock pulses.
A write access and the instruction DEL_DIA is internally suppressed (i.e internal
registers will not be affected) in all cases where at the rising (inactive) edge of SS the
number of falling edges applied to the SPI input SCK during the access is not equal to 16.
A write access is also internally suppressed (i.e internal registers will not be affected) if
at the rising (inactive) edge of SS a 17th bit is submitted (SCK=‘1’).
After the bits CPAD1,0 and INSTR (4-0) have been sent from the microcontroller
TLE6244X is able to check if the instruction code is valid. If an invalid instruction is
detected, any modification on a register of TLE6244X is not allowed and the data
byte ‘FFh’ is transmitted after having sent the verification byte. If a valid read instruction is
detected the content of the corresponding register is transmitted to the controller after having
sent the verification byte (even if bit INSW afterwards is wrong). If a valid write instruction is
detected the data byte ’00h’ is transmitted to the controller after having sent the verification
byte (even if bit INSW afterwards is wrong) but modifications on any register of TLE6244 are
not allowed until bit INSW is valid, too.
If an invalid instruction is detected bit TRANS_F in the following verification byte is set to
’High’. This bit must not be cleared before it has been sent to the microcontroller.If TLE6244X and additional IC’s are connected to one common slave select, they are
distinguished by the chip address (CPAD1, CPAD0). If an IC with 32bit-transmission-format is
selected, TLE6232 must not be activated, even if slave select is set to ’low’ and
the first two bits of the third byte of the 32bit-transmission are identical to the chip address
of TLE6244X.
During the transmission of CPAD1 and CPAD0 the data output SO remains in tristate (see
timing diagram of the SPI in chapter 3.9. ).
SPI access format:
Verification byte:
SPI Instructions
1.6.1 Serial/Parallel Control Serial/Parallel Control of the Power Stages 1...16 and Serial Control (SPI) of the Power Stages 17 and
18:
The registers MUX_REG1/2 and the bmux-bit prescribe parallel control or serial control (SPI or µsec-
bus) of the power stages.
(SPI-Instructions: WR_MUX1...2, RD_MUX1...2, WR_SCON1...3, RD_SCON1...3)The following table shows the truth table for the control of the power stages 1...18. The registers
MUX_REG1, 2 prescribe parallel-control or serial control of the power stages. The registers
SCON_REG1...3 prescribe the state of the power stage in case of SPI-serial control. BMUX deter-
mines parallel control or control by µsec-bus.
For the power stages 17 and 18 control is exclusively possible via SCON17/18. IN17/18 and
MUX17/18 do not exist. BMUX has no function for OUT17/18.
Exception: OUT8 is on (active) if IN8 is set to logic ‘1’ (and off if IN8 is set to logic ‘0’) in case of
parallel access.
Note: OUT8 cannot be controlled by the µsec-Bus. Refer to section 1.7.
Description of the SPI Registers
1.6.2 Diagnostics/Encoding of Failures
Description of the SPI Registers
(SPI Instructions: RD_DIA1...5)
1.6.3 Configuration
The µsec-bus is enabled by this register. In addition the shut off at SCB can be configured for the
power-stages OUT9, OUT10 and OUT15... OUT18.
Description of the µsec-bus see chapter 1.7
1.6.4 Other
Reading the IC Identifier (SPI Instruction: RD_IDENT1):
Reading the IC revision number (SPI Instruction: RD_IDENT2):
Reset of the Diagnostic Information (SPI Instruction: DEL_DIA):
Resets the 5 diagnostic registers DIA_REG1...5 to FFH and the common overtemperature flag in regis-
ter STATCON_REG (Bit4) to High. These bits are only cleared by the DEL_DIA instruction when there
is no failure entry at the input of the registers.
Access is performed like a writing access with any data byte.
In the case a power stage is shut off because of SCB, the output is activated again by the DEL_DIA
instruction and the filtering-time is enabled. Therefore in case of SCB the output is activated and shut
off after the shutoff delay.
For a power stage in the current limitation mode, the current limitation mode is left, if a DEL_DIA
instruction has been received. If there is still the condition for SCB the current limitation mode
is entered again.
On the following pages the conditions for set and reset of the SCB report in DIA_REGx is shown in
several schematics. The signal „power stage control“ is generated as follows: INi=“ON“SPI=“ON“µsec=“ON“
Reading Input1 (SPI Instruction: RD_INP1)
Reading Input2 (SPI Instruction: RD_INP2):
The input pins IN1..IN5 and IN8...IN15 can be used as input port expander by reading the status of
the input pins using the SPI-commands RD_INP1/2. If the µsec-bus-interface is enabled (BMUX=0) the
pull-up current sources at the input IN1..5 and IN9..15 are disabled. If BMUX=1 the pullup current
sources at these pins are enabled. The pull-up/pull-down current sources of the other input pins are
not effected by the bit BMUX.
On executing the read instruction on RD_INP1/2, the present status (not latched) of the input pins INx is
read back (exception: bit IN8 represents the inverted status of input pin IN8).
Reading the State resp. the Configuration:
(SPI Instructions: WR_STATCON, RD_STATCON)
The µsec-bus-interface is one of three possibilities to control the power stages. OUT1...OUT7
and OUT9...OUT16 are influenced by the reset input RST. If RST is set to Low, these power
stages are switched off. After reset they are controlled by the SPI (default initialization of
TLE6244X). Power stage 8 however is not influenced by the reset input if it’s controlled by IN8
and UVDD > 3,5V. Alternatively these outputs can be controlled either by the pins IN1...IN16 or by
the µsec-bus interface. Exception: OUT8 can be controlled by IN8 or by the SPI-interface only.
The bit ’Bus-Multiplex’ (BMUX) in the SPI register CONFIG prescribes parallel access (IN1...IN7,
IN9...IN16) or µsec-bus control (see figure below). Exception: If BMUX is set to ‘0’ only the power-
stages OUT1...OUT7 and OUT9...OUT16 are controlled by the µsec-bus.
Main features:
- 16 data bits for each data-frame (at the pin FDA)
- 16 clock-pulses for each data-frame (at the pin FCL)
- clock frequencyTLE6244: 0...16 MHz
- one sync -input (pin SSY) to latch the input data stream
- input level interface same as for IN6, IN7, IN16
- no error correction
When the bit BMUX in CONFIG is set to Low, the power stages 1...7 and 9...16 are controlled by
the µsec-bus-interface on condition that registers MUX_REG1/2 are configured for serial access.
The received µsec-bus bit stream (D0... D15) is latched into a 16-bit register by the rising edge at
SSY. Power stages 1...7 and 9...16 are switched according to bits D0...D7 and D9...D15:
Bit Dx = 0:Power stage OUTx is switched on
Bit Dx = 1:Power stage OUTx is switched off
State of reset:FFFFH
Because the power stage 8 is not controlled by the µsec-bus-interface, the corresponding bit D8
can be used as test bit, that can be read back by the SPI-interface (see register RD_INP1).
If the µsec-bus-interface is used to control the power stages, the input pins IN1..IN5 and
IN8...IN15 can be used as input port expander by reading the status of the input pins by the SPI-
commands RD_INP1/2.
To avoid an „open load“ fault indication an unused power switch has to be connected to an exter-
nal pull up resistor connected to UUB or has to be switched on by the input pin or via SPI or the
µsec-bus-interface.
RPull-up,max = (UBRmin - Udrop,max - UthresOL,max) / Idiag,max
UBRmin is the required minimum battery voltage for diagnostic function of the ECU. The drop volt-
age is composed of the drop voltage of the regulator and the drop voltage of the reverse protec-
tion circuit of the regulator resp. the forward voltage of a reverse protection diode.
Attention:
This equation also applies to power switches that are used as signal drivers (pull up resistor
inside ECU or outside ECU): the permissible pull up resistance without a wrong diagnostic infor-
mation is calculated by the same equation. On dimensioning the pull up resistance in combination
with the diagnostic current, in applications as signal drivers attention must be paid especially to
the required high level (also for low battery voltage).IdiagPull-up
UBRUUB
UdropUBatt
1.9.1 Power StagesINiH
UINiLINi
If the output is controlled via SPI the timing starts with the positive slope at SSIf the output is controlled by the µsec-bus, the timing starts with the pos. slope of SSY*) With ohmic load, UCLi = UBatt
0.8UCLi*)
0.8UBATT
0.2UBATT
UCLiOUTi
UBATT
0.2UCLi
Overview:
The VDD-monitoring generates a „low“ signal at the bidirectional pin ABE if the 5V supply volt-
age at pin VDD is out of the permissible range of 4.5V...5.5V. On ABE = low the power stages of
TLE6244X are switched off. Exception: OUT8 is not switched off in case of parallel control via
IN8 by the VDD monitoring undervoltage threshold, but by a threshold of 3.5V at VDD.
On shorting pin ABE to VDD or UBATT (≤ 36V), the power stages will be switched off in case of
undervoltage or overvoltage at pin VDD in spite of ABE = high.
The behavior of the ABE level on the return of VDD out of the undervoltage range into the cor-
rect range is not configurable. At the transition from undervoltage to normal voltage the signal
at pin ABE goes high after a filtering time is expired. The behavior of the ABE level on the
return of VDD out of the overvoltage range into the correct range is configurable in
STATCON_REG, Bit5. At the transition from overvoltage to normal voltage the signal at pin ABE
goes high either after a filtering time (OV not latched) or after a SPI writing instruction (OV
latched, state after reset).
On undervoltage condition the signal at pin ABE goes high after a filtering time is expired. On
overvoltage condition pin ABE goes high either after a filtering time or after a SPI writing instruc-
tion. Before this SPI instruction is sent to TLE6244X appropriate tests can be carried out by the
controller.
If the voltage at pin VDD is below the lower limit or is resp. was above the upper limit, this can
be read out by the SPI instruction RD_STATCON.
VDD-monitoring has no influence on SCON_REGx, MUX_REGx, DIA_REGx, CONFIG and
INP_REGx.
If output stages are switched off by the internal over-/undervoltage detection or by externally
applying a low signal at the ABE pin, no failure storage (DIAREG1...5) may occur.
Description in Detail:
STATCON_REG
Bit 71:Normal operationTest of VDD threshold
Access by controller: read/write
State of reset: 1
Bit 61:Testing the lower threshold (if bit 7 = 0)Testing the upper threshold (if bit 7 = 0)
Access by controller: read/write
State of reset: 1
Bit 51:ABE latched after overvoltageABE deactivated immediately after the disappearance of the overvoltage
Access by controller: read/write
State of reset: 1
Bit 2Reading out the level at pin ABE
Access by controller: read only
Bit 11:no undervoltage at pin VDDundervoltage at pin VDD
Access by controller: read only
Bit 01:no overvoltage at pin VDDovervoltage at pin VDD resp. state of overvoltage still stored
Access by controller: read only
Upper threshold:
By writing 000xxxxxb in the register STATCON_REG the overvoltage threshold is reduced by
0.8V. In STATCON_REG Bit 0 has to be LOW then.
After writing 110xxxxxb in the register STATCON_REG Bit 0 in STATCON_REG must be HIGH
again.
Lower threshold:
By writing 010xxxxxb in the register STATCON_REG the overvoltage threshold is increased by
0.8V. In STATCON_REG Bit 1 has to be LOW then.
After writing 110xxxxxb in the register STATCON_REG Bit 1 in STATCON_REG must be HIGH
again.
Example of configuration:
Requirement: After overvoltage ABE is to be LOW;
After overvoltage a self-test is carried out by the ECU, afterwards ABE is deactivated.
Register STATCON_REG is set to 111xxxxxb during driving cycle.
When ABE becomes active, overvoltage can be detected by reading out STATCON_REG.
After the ECU’s self-test a reset condition is achieved by writing 110xxxxxb into the register
STATCON_REG. This reset is only possible after disappearance of the overvoltage condition
because the set input is dominant. The reset signal is withdrawn by writing 111xxxxxb.
