TLE6230GP . ,Smart Low Side SwitchesApplications(individually) 1 A• Parallel Inputs High or Low ActiveProgrammable• General Fault Flag• ..
TLE6232GP ,Smart Low Side SwitchesApplications Output current (Channel 1-4) I 2 A D(NOM) • General Fault Flag (Channel 5,6) I 1 A D ..
TLE6232GP ,Smart Low Side SwitchesFeatures Product Summary • Short Circuit Protection up to 24 V • Over-tempera ..
TLE6232GP. ,Smart Low Side SwitchesGeneral description Six Channel Low-Side Switch in Smart Power Technology (SPT) with a Serial Perip ..
TLE6232GP.. ,Smart Low Side SwitchesApplications • Switch for Automotive and Industrial System • Solenoids, Relays and Resistive Loads ..
TLE6236G ,Smart Low Side SwitchesGeneral descriptionOctal Low-Side Switch in Smart Power Technology (SPT) with a SerialPeripheral In ..
TMP87CK40AN , CMOS 8-Bit Microcontroller
TMP87CM23AF , CMOS 8-BIT MICROCONTROLLER
TMP87CM36N , CMOS 8 BIT MICROCONTROLLER
TMP87CM40AN , CMOS 8-Bit Microcontroller
TMP87CM53F , CMOS 8-BIT MICROCONTROLLER
TMP87CM70AF , CMOS 8-BIT MICROCONTROLLER
TLE6230GP-TLE6230GP .
Smart Low Side Switches
Data Sheet TLE 6230 GP
Smart Octal Low-Side Switch
Features Product SummaryShort Circuit Protection
• Overtemperature Protection
• Overvoltage Protection16 bit Serial Data Input and Diagnos-
tic Output (2 bit/ch. acc. SPI protocol)Direct Parallel Control of Four Chan-
nels for PWM ApplicationsParallel Inputs High or Low Active
ProgrammableGeneral Fault FlagLow Quiescent CurrentCompatible with 3,3 V Micro Controllers
Electostatic Discharge (ESD) Protection ApplicationµC Compatible Power Switch for 12 V and 24V ApplicationsSwitch for Automotive and Industrial SystemsSolenoids, Relays and Resistive Loads
• Robotic Controls
General descriptionOctal Low-Side Switch in Smart Power Technology (SPT) with a Serial Peripheral Interface (SPI) andeight open drain DMOS output stages. The TLE 6230 GP is protected by embedded protection func-
tions and designed for automotive and industrial applications. The output stages are controlled via an
SPI Interface. Additionally four channels can be controlled direct in parallel for PWM applications.
Therefore the TLE 6230 GP is particularly suitable for engine management and powertrain systems.
Block Diagram
RESETFAULT
SCLK
IN1
IN2
IN3
IN4
OUT8
PRG
Data Sheet TLE 6230 GP
Detailed Block DiagramFAULTRESET
IN2
SCLK
IN1
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
IN3
IN4
PRG
GND
Data Sheet TLE 6230 GP
Pin Description Pin Configuration (Top view)
PinFunctionHeat Slug internally connected to ground pins
GNDGNDNCNC
OUT1OUT8
OUT2OUT7
IN1NC
IN2NCSI
RESETSCLKSO
PRGFAULTIN3NC
IN4NC
OUT3OUT6
OUT4OUT5NCNC
GNDGND
Power SO 36
Data Sheet TLE 6230 GP
Maximum Ratings for Tj = – 40°C to 150°C RI=internal resistance of the load dump test pulse generator LD2002) V is setup without DUT connected to the generator per ISO 7637-1 and DIN 40 839.
PCB with heat pipes,
backside 6 cm2 cooling area Minimum footprint
Data Sheet TLE 6230 GP
Electrical Characteristics
1. Power Supply, ResetV
2. Power Outputs
3. Digital Inputs
4. Digital Outputs (SO, FAULT) For VS < 4.5V the power stages are switched according the input signals and data bits or are definitely switched
Data Sheet TLE 6230 GP
Electrical Characteristics cont.VS = 4.5 to 5.5 V ; Tj = - 40 °C to + 150 °C ; Reset = H
(unless otherwise specified)
5. Diagnostic Functions
6. SPI-Timing This parameter will not be tested but guaranteed by design
Data Sheet TLE 6230 GP
Functional DescriptionThe TLE 6230 GP is an octal-low-side power switch which provides a serial peripheral inter-
face (SPI) to control the 8 power DMOS switches, as well as diagnostic feedback. The powertransistors are protected against short to VBB, overload, overtemperature and against over-
voltage by an active zener clamp.
The diagnostic logic recognizes a fault condition which can be read out via the serial diagnos-
tic output (SO).
Circuit Description
Output Stage ControlEach output is independently controlled by an output latch and a common reset line, which
disables all eight outputs. Serial data input (SI) is read on the falling edge of the serial clock. Alogic high input data bit turns the respective output channel ON, a logic low data bit turns it
OFF. CS must be low whilst shifting all the serial data into the device. A low-to-high transition
of CS transfers the serial data input bits to the output buffer.
Special conditions for Channel 1 to 4:In addition to the serial control of the outputs it is possible to control channel 1 to channel 4
directly in parallel for PWM applications. These inputs are high or low active (programmable
via PRG pin) and ANDed with the SPI control bit.
The table shows the AND-operation of the parallel
input pin (here active high) and the corresponding
SPI bit. For an application where the parallel input is
always "ON", it is possible to switch the channel
OFF via the SPI bit, e.g. for diagnosis in OFF-state.
SPI Priority for OFF-stateOperation with parallel inputs: Set SPI bits to logic high.Operation via SPI: Connect parallel inputs to logic high (if programmed to active high).
PRG - Program pin. PRG = High (VS): Parallel inputs Channel 1 to 4 are high active
PRG = Low (GND):Parallel inputs Channel 1 to 4 are low active.
If the parallel input pins are not connected (independent of high or low activity) it is guaranteed
that the channels 1 to 4 are switched OFF.
PRG pin itself is internally pulled up when it is not connected.OUT 1 - 4
Data Sheet TLE 6230 GP
Power Transistor Protection Functions8)Each of the eight output stages has its own zener clamp, which causes a voltage limitation at
the power transistor when solenoid loads are switched off. The outputs are provided with a
current limitation set to a minimum of 1 A. The continuous current for each channel is 500 mA
(all channels ON).Each output is protected by embedded protection functions. In the event of an overload or
short to supply, the current is internally limited and the corresponding bit combination is set
(early warning). If this operation leads to an overtemperature condition, a second protection
level (about 170 °C) will change the output into a low duty cycle PWM (selective thermal shut-
down with restart) to prevent critical chip temperatures.
SPI Signal Description
CS - Chip Select. The system microcontroller selects the TLE 6230 GP by means of the CS
pin. Whenever the pin is in a logic low state, data can be transferred from the µC and vice
versa.
CS High to Low transition:-diagnostic status information is transferred from the power
outputs into the shift register.serial input data can be clocked in from then on- SO changes from high impedance state to logic high or low state corresponding to the SO bits
CS Low to High transition: -transfer of SI bits from shift register into output buffers - reset of diagnosis register
To avoid any false clocking the serial clock input pin SCLK should be logic low state during
high to low transition of CS. When CS is in a logic high state, any signals at the SCLK and SI
pins are ignored and SO is forced into a high impedance state.
SCLK - Serial Clock. The system clock pin clocks the internal shift register of the TLE
6230 GP. The serial input (SI) accepts data into the input shift register on the falling edge of
SCLK while the serial output (SO) shifts diagnostic information out of the shift register on the
rising edge of serial clock. It is essential that the SCLK pin is in a logic low state whenever
chip select CS makes any transition. The number of clock pulses will be counted during a
chip select cycle. The received data will only be accepted, if exactly 16 clock pulses were
counted during CS is active.
SI - Serial Input. Serial data bits are shifted in at this pin, the most significant bit first. SI infor-mation is read in on the falling edge of SCLK. Input data is latched in the shift register and
then transferred to the control buffer of the output stages.
The input data consists of two bytes - a "control byte” followed by a "data byte". The control
byte contains the information as to whether the data byte will be accepted or ignored (see di-agnostics section). The data byte contains the input information for the eight channels. A logic
