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TLE6225G-TLE6225G ..
Smart Low Side Switches
Data Sheet TLE 6225G
Smart Quad Low-Side Switch
Features Product SummaryShorted circuit protection
• Overtemperature protection
• Overvoltage protectionOpen Load DetectionDirect parallel control of the inputsInputs high or low active programmableGeneral fault flagVery low standby quiescent currentCompatible with 3V microcontrollers
Electostatic discharge (ESD) protection ApplicationµC compatible power switch for 12 V applicationsSwitch for automotive and industrial systemsLine, relay or lamp driver
General descriptionQuad channel Low-Side Switch in Smart Power Technology (SPT) with four separate inputsand four open drain DMOS output stages. The TLE 6225 G is protected by embedded protec-
tion functions and designed for automotive and industrial applications, to drive lines, lamps
and relays.
Block Diagram
Data Sheet TLE 6225G
Pin Description Pin Configuration (Top view)IN1PRG
IN2OUT1
FAULTOUT2
GNDGND
GNDGND
GNDGND
GNDGNDOUT3
IN3OUT4
IN4ENA
P-DSO-20-6
Data Sheet TLE 6225G
Maximum Ratings for Tj = – 40°C to 150°C Data Sheet TLE 6225G
Electrical Characteristics
1. Power SupplyVS4.5V
2. Power Outputs
3. Digital Inputs (IN1 – IN4, ENA, PRG)
4. Digital Output (FAULT)
5. Diagnostic Functions
Data Sheet TLE 6225G
Functional DescriptionThe TLE 6225 G is a quad channel low-side switch with four power DMOS stages. The power
transistors are protected against short to VBB, overload, overtemperature and against over-
voltage by zenerclamp.
The diagnostic logic recognises a fault condition which is indicated by a fault flag.
Circuit Description
Output Stage ControlEach output is independently controlled by an input pin and a common enable line, which en-
ables/disables all four outputs. The parallel inputs are high or low active depending on thePRG pin. If the parallel input pins are not connected (independent of high or low activity) it is
guaranteed that the outputs 1 to 4 are switched OFF. ENA - and PRG - pin itself are internally
pulled down when they are not connected.
ENA - Enable pin.ENA = High:Active mode. Channels are enabled
ENA = Low (GND):Sleep mode. Channels are switched off. Less than
1 µA current consumption.
PRG - Program pin. PRG = High: Parallel inputs Channel 1 to 4 are high activePRG = Low (GND):Parallel inputs Channel 1 to 4 are low active.
Power TransistorsEach of the four output stages has its own zenerclamp. This causes a voltage limitation at the
power transistors when inductive loads are switched off. The outputs are provided with a cur-rent limitation set to a minimum of 500 mA.
Each output is protected by embedded protection functions3). In the event of an overload or
short to supply, the current is internally limited. If this operation leads to an overtemperature
condition, a second protection level (about 170 °C) will turn the effected output into a PWM-
mode (selective thermal shutdown with restart) to prevent critical chip temperatures. The tem-perature hysteresis is typically 10K.
DiagnosticThe FAULT pin is an open drain output. The logic status depends on the programming pinPRG.
FAULT - pin. FAULT = High no fault @ PRG = High
FAULT = Low no fault @ PRG = Low
Data Sheet TLE 6225G
Diagnostic TableX = not relevant
*selective thermal shutdown for each channel at overtemperature
Fault DistinctionOpen load/short to ground is recognised in OFF-state. Overtemperature as a result of an
overload or short to battery can only arise in ON-state. If there is only one fault at a time, it ispossible to distinguish which channel is affected with which fault.
