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TLE6220GP-TLE6220-GP
Smart Low Side Switches
Data Sheet TLE 6220 GP
Smart Quad Low-Side Switch
Features Product SummaryShort Circuit Protection
• Overtemperature Protection
• Overvoltage Protection8 bit Serial Data Input and Diag-
nostic Output (SPI protocol)Direct Parallel Control of Four
Channels for PWM ApplicationsCascadable with Other Quad SwitchesLow Quiescent CurrentµC Compatible Input
Electostatic Discharge (ESD) Protection ApplicationµC Compatible Power Switch for 12 V and 24 V ApplicationsSwitch for Automotive and Industrial SystemSolenoids, Relays and Resistive Loads
• Injectors
• Robotic controls
General DescriptionQuad Low-Side Switch in Smart Power Technology (SPT) with a Serial Peripheral Interface (SPI) and
four open drain DMOS output stages. The TLE 6220 GP is protected by embedded protection func-
tions and designed for automotive and industrial applications. The output stages can be controlled di-rect in parallel for PWM applications (injector coils), or through serial control via the SPI. Therefore the
TLE 6220 GP is particularly suitable for engine management and powertrain systems.
Block Diagram
FAULTRESET
SCLK
IN1
IN2
IN3
IN4
OUT4
PRG
Data Sheet TLE 6220 GP
Pin Description Pin Configuration (Top view)FunctionHeat slug internally connected to ground pins
GNDGND
IN2IN3
OUT1OUT4SI
RESETSCLKSO
PRGFAULT
OUT2OUT3
IN1IN4
GNDGND
Power SO-20
Data Sheet TLE 6220 GP
Maximum Ratings for Tj = – 40°C to 150°C RI=internal resistance of the load dump test pulse generator LD2002) V is setup without DUT connected to the generator per ISO 7637-1 and DIN 40 839.
PCB with heat pipes,backside 6 cm2 cooling area
Minimum footprint
Data Sheet TLE 6220 GP
Electrical CharacteristicsVS = 4.5 to 5.5 V ; Tj = - 40 °C to + 150 °C ; Reset = H
(unless otherwise specified)
1. Power Supply, ResetV
2. Power Outputs
3. Digital Inputs
4. Digital Outputs (SO,FAULT) 4 For VS < 4.5V the power stages are switched according the input signals and data bits or are definitely switched
off. This undervoltage reset gets active at VS = 3V (typ. value) and is guaranteed by design.
Data Sheet TLE 6220 GP
Electrical Characteristics cont.VS = 4.5 to 5.5 V ; Tj = - 40 °C to + 150 °C ; Reset = H
(unless otherwise specified)
5. Diagnostic Functions
6. SPI-Timing This time is necessary between two write accesses. To get the correct diagnostic information, the transfer delay
Data Sheet TLE 6220 GP
Functional DescriptionThe TLE 6220 GP is an quad-low-side power switch which provides a serial peripheral inter-
face (SPI) to control the 4 power DMOS switches, as well as diagnostic feedback. The power
transistors are protected against short to VBB, overload, overtemperature and against over-voltage by an active zener clamp.
The diagnostic logic recognises a fault condition which can be read out via the serial diagnos-
tic output (SO).
Circuit Description
Power Transistor Protection Functions9)
Each of the four output stages has its own zener clamp, which causes a voltage limitation at
the power transistor when solenoid loads are switched off. The outputs are provided with acurrent limitation set to a minimum of 3 A. The continuous current for each channel is 1A (all
channels ON; depending on cooling).
Each output is protected by embedded protection functions. In the event of an overload or
short to supply, the current is internally limited and the corresponding bit combination is set
(early warning). If this operation leads to an overtemperature condition, a second protectionlevel (about 170 °C) will change the output into a low duty cycle PWM (selective thermal shut-
down with restart) to prevent critical chip temperatures.
SPI Signal Description
CS - Chip Select. The system microcontroller selects the TLE 6220 GP by means of the CSpin. Whenever the pin is in a logic low state, data can be transferred from the µC and vice
versa.
CS High to Low transition: - Diagnostic status information is transferred from the power
outputs into the shift register.Serial input data can be clocked in from then on.
- SO changes from high impedance state to logic high or low state corresponding to the SO bits.
CS Low to High transition: - Transfer of SI bits from shift register into output buffers - Reset of diagnosis register.
To avoid any false clocking the serial clock input pin SCLK should be logic low state during
high to low transition of CS. When CS is in a logic high state, any signals at the SCLK and SI
pins are ignored and SO is forced into a high impedance state.
Data Sheet TLE 6220 GP
SCLK - Serial Clock. The system clock pin clocks the internal shift register of the TLE
6220 GP. The serial input (SI) accepts data into the input shift register on the falling edge ofSCLK while the serial output (SO) shifts diagnostic information out of the shift register on the
rising edge of serial clock. It is essential that the SCLK pin is in a logic low state whenever
chip select CS makes any transition.
SI - Serial Input. Serial data bits are shifted in at this pin, the most significant bit first. SI infor-mation is read in on the falling edge of SCLK. Input data is latched in the shift register and
then transferred to the control buffer of the output stages.
The input data consists of one byte, made up of four control bits and four data bits. The con-
trol word is used to program the device, to operate it in a certain mode as well as providing
diagnostic information (see page 11). The four data bits contain the input information for thefour channels, and are high active.
SO - Serial Output. Diagnostic data bits are shifted out serially at this pin, the most significantbit first. SO is in a high impedance state until the CS pin goes to a logic low state. New diag-
nostic data will appear at the SO pin following the rising edge of SCLK.
RESET- Reset pin. If the reset pin is in a logic low state, it clears the SPI shift register and
switches all outputs OFF. An internal pull-up structure is provided on chip. As long as the reset
pin is low the device is in low quiescent current mode and the supply current is reduced to typ.
20µA.
Output Stage ControlThe four outputs of the TLE 6220 GP can either be controlled in parallel (IN1...IN4), or via the
Serial Peripheral Interface (SPI).
Parallel ControlA Boolean operation (either AND or OR) is performed on each of the parallel inputs and re-spective SPI data bits, in order to determine the states of the respective outputs. The type of
Boolean operation performed is programmed via the serial interface.
The parallel inputs are high or low active depending on the PRG pin. If the parallel input pins
are not connected (independent of high or low activity) it is guaranteed that the outputs 1 to 4
are switched OFF. PRG pin itself is internally pulled up when it is not connected.
PRG - Program pin. PRG = High (VS): Parallel inputs Channel 1 to 4 are high active
PRG = Low (GND):Parallel inputs Channel 1 to 4 are low active.
Data Sheet TLE 6220 GP
Serial Control of the Outputs: SPI protocolEach output is independently controlled by an output latch and a common reset line, which
disables all four outputs. The Serial Input (SI) is read on the falling edge of the serial clock. A
logic high input 'data bit' turns the respective output channel ON, a logic low 'data bit' turns it
OFF. CS must be low whilst shifting all the serial data into the device. A low-to-high transition
of CS transfers the serial data input bits to the output control buffer.
As mentioned above, the serial input byte consists of a 4 bit control word and a 4 bit dataword. Via the control word, the specific mode of the device is programmable.
MSBLSB ������
Bits DataBits Control
DDDDCCCC : Serial input byte
Five specific control words are recognised, having the following functions: LLLL XXXX
Note:'X' means 'don't care', because this bit will be ignored
'D' represents the data bit, either being H (=ON) or L (=OFF)
1. LLLL XXXX -Diagnosis only
By clocking in this control byte, it is possible to get pure diagnostic information (two bits perchannel) in accordance with Figure 1 (page 11). The data bits are ignored, so that the state of
the outputs are not influenced. This command is only active once unless the next control
command is again "Diagnosis only".
2. HHLL XXXX - Reading back of input, and ‘1-bit Diagnosis’
If the TLE 6220 GP is used as bare die in a hybrid application, it is necessary to know if properconnections exist between the µC-port and parallel inputs. By entering ‘HHLL’ as the control
word, the first four bits of the SO give the state of the parallel inputs, depending on the µC
signals. By comparing the four IN-bits with the corresponding µC-port signal, the necessary
connection between the µC and the TLE 6220 can be verified - i.e. ‘read back of the inputs’.
The second 4-bit word fed out at the serial output contains ‘1-bit’ fault information of the out-puts ( H = no fault, L = fault ). In the expression given below for the output byte, ‘FX’ is the
fault bit for channel X.
MSB LSBIN4 IN3 IN2 IN1 F4 F3 F2 F1 : Serial Output byte
Data Sheet TLE 6220 GP3. HLHL XXXX -Echo-function of SPI
To check the proper function of the serial interface the TLE 6220 GP provides a "SPI Echo
Function". By entering HLHL as control word, SI and SO are connected during the next CS
period. By comparing the bits clocked in with the serial output bits, the proper function of the
SPI interface can be verified. This internal loop is only closed once (for one CS period).
4. LLHH DDDD -OR operation, and ‘full diagnosis’With LLHH as the control word, each of the input signals IN1...IN4 are 'OR'ed with the corre-
sponding data bits (DDDD).
This OR operation enables the serial interface to switch the channel ON, even though the cor-responding parallel input might be in the off state.
SPI Priority for ON-StateAlso parallel control of the outputs is possible without an SPI input.
