TLE6217G ,Vehicle Stability ICsApplications)• Separate Diagnostic Pin for Each Channel Output current I 2 x 5 AD 1,2• Power - SO 2 ..
TLE6220GP ,Smart Low Side SwitchesGeneral DescriptionQuad Low-Side Switch in Smart Power Technology (SPT) with a Serial Peripheral In ..
TLE6220-GP ,Smart Low Side SwitchesFeatures Product Summary• Short Circuit ProtectionSupply voltage V 4.5 – 5.5 VS• ..
TLE6225 ,Smart Quad Low-Side SwitchBlock DiagramENAVS FAULTPRGGND VSVDiagnostic, bbProtectionIN1Over Temp.as Ch. 1LogicOpen Loadas Ch. ..
TLE6225G ,Smart Low Side Switchesapplications P- DSO 20-6• Switch for automotive and industrial systems Ordering Code:• Line, relay ..
TLE6225G ,Smart Low Side SwitchesBlock DiagramENAVS FAULTPRGGND VSVDiagnostic, bbProtectionIN1Over Temp.as Ch. 1LogicOpen Loadas Ch. ..
TMP87CK38N , CMOS 8-BIT MICROCONTROLLER
TMP87CK40AN , CMOS 8-Bit Microcontroller
TMP87CM23AF , CMOS 8-BIT MICROCONTROLLER
TMP87CM36N , CMOS 8 BIT MICROCONTROLLER
TMP87CM40AN , CMOS 8-Bit Microcontroller
TMP87CM53F , CMOS 8-BIT MICROCONTROLLER
TLE6217G
Vehicle Stability ICs
Smart Quad Channel Low-Side Switch
Features Product SummaryShorted Circuit ProtectionOvertemperature Protection· Overvoltage ProtectionParallel Control of the Inputs (PWM Applications)· Separate Diagnostic Pin for Each ChannelPower - SO 20 - Package with integrated cooling area· Standby mode with low current consumptionµC compatible Input· Electrostatic Discharge (ESD) Protection
ApplicationAll kinds of resistive and inductive loads (relays, electromagnetic valves)· µC compatible power switch for 12 and 24 V applicationsSolenoid control switch in automotive and industrial control systems· Robotic Controls
General descriptionQuad channel Low-Side-Switch (2x5A/2x3A) in Smart Power Technology (SPT) with four separate in-
puts and four open drain DMOS output stages. The TLE 6217 GP is fully protected by embedded pro-
tection functions and designed for automotive and industrial applications. Each channel has its own
status signal for diagnostic feedback. Therefore the TLE 6217 GP is particularly suitable for ABS orPowertrain Systems.
Block Diagram
ST1
ST2
IN1
IN2
IN3
IN4
OUT4
STBY
Pin Configuration (Top view)
Pin DescriptionHeat slug internally connected to ground pins
P - DSO - 20 - 12
Detailed Block DiagramST4
IN4
ST1
IN1
ENA
ST3
IN3
ST2
IN2
STBY
OUT1
OUT4
OUT2
OUT3
Maximum Ratings for Tj = – 40°C to 150°CThe maximum ratings may not be exceeded under any circumstances, not even momentarily and
individually, as permanent damage to the IC will result.
UnitVVmJ
Ambient thermal conditions
Electrical Characteristics
1. Power Supply (VS)Supply current (Outputs ON)mAmAµA
2. Power OutputsVµAmA
3. Digital Inputs (IN1, IN2, IN3, IN4, ENA)mVµA
4. Digital Status Outputs (ST1 - ST4) Open Drain Electrical Characteristics
5. Standby Input (STBY)
6. Diagnostic FunctionsmA°C
Application DescriptionThis IC is especially designed to drive inductive loads (relays, electromagnetic valves).
Integrated clamp-diodes limit the output voltage when inductive loads are discharged.
Four open-drain logic outputs indicate the status of the integrated circuit. The following conditions are
monitored and signalled:
- Overloading of output (also shorted load to supply) in active mode
- Open and shorted load to ground in active and inactive mode
- Overtemperature
Circuit Description
Input CircuitsThe control and enable inputs, both active high, consist of schmitt triggers with hysteresis. All inputs areprovided with pull-down current sources. Not connected inputs are interpreted as low and the respective
output stages are switched off.
In standby mode (STBY = LOW) the current consumption is greatly reduced.The circuit is active when STBY = HIGH.
If the standby function is not used, it is allowed to connect the standby pin directly to VS.
Status Signals: The status signals are undefined for 2ms after a power up event or a STBY low to high
transition.
Output StagesThe four power outputs consist of DMOS-power transistors with open drains. The output stages are
short circuit protected throughout the operating range. Each output has it's own zenerclamp. This
causes a voltage limitation at the power transistor when inductive loads are switched off.
Parallel to the DMOS transistors there are internal pull down current sources. They are provided to de-tect an open load condition in the off state. They will be disconnected in the standby mode.
Due to EMI measures there is an internal zenerclamp in parallel to the output stage. It gets active above
33V drain source voltage. This leads to an increasing leakage current up to 1 mA @ VDS = 40V.
Protective CircuitsThe outputs are protected against current overload and overtemperature. If the output current increasesabove the overload detection threshold IQO for a longer time then tDSO or the temperature increasesabove Tth, then the power transistor is immediately switched off. It remains off until the control signal at
the input is switched off and on again.
Fault DetectionThe status outputs indicate the switching state of the output stage. Under normal conditions is: ST = low
Þ Output off; ST = high Þ Output on. If an error occurs, the logic level of the status output is inverted,
as listed in the diagnostic table.
If current overload or overtemperature occurs for a longer time than tDSO, the fault condition is latched
Open load is detected for all four channels in on and off mode.
In the on mode the load current is monitored. If it drops below the specified threshold value IQU then anopen load condition is detected.
In the off mode, the output voltage is monitored. An open load condition is detected when the output
voltage of a given channel is below the threshold VDS(OL), which is typ. 33 % of the supply voltage VS. Toprevent an open load diagnosis in case of transient Voltages on the outputs the open load detection in
off mode uses a filter of typ. 30µs.
Status output at pulse width operationIf the input is operated with a pulsed signal, the status does not follow each single pulse of the input sig-
nal. An internal delay tD of typ. 1.2ms (min 500 ms) enables a continuous status output signal. See the
timing diagrams on the following pages for further information.
This internal status delay simplifies diagnostic software for pwm applications.
Diagnostic TableIn general the status follows the input signal in normal operating conditions.
If any error is detected the status is inverted.
Note 1) : overload/short-to-supply/overtemperature - events shorter than min. time tDSO specified in 2.10
will not be latched and not reported at the status pin.
Note 2): to reset latched status-output in case of overload/short-to-supply/overtemperature the control
input has to go low and stay low for longer than max. Input suppression time tD-IN specified in 2.13 of the
characteristics
Failure Situations and Status Report
Logic Block Diagram
Open load "on"0.....open load
1.... normal cond.
Open load "off"1.....open load
0.....normal cond.
Overload0.....overload1.....normal cond.
Input1....On
0... Off
ENA1....enabled
0... disabled
Overtemperature1.....overtemperature
0.....normal cond.
Gate Driver1... Output0....Output
Off
Status
0....High
Delay DOUT
OUT
Filter
