TL16C554AIPN ,Quad UART with 16-Byte FIFOs
TL16C554FN ,Quad UART with 16-Byte FIFOs SLLS165G − JANUARY 1994 − REVISED MARCH 2006 Int ..
TL16C554FNR ,Quad UART with 16-Byte FIFOs SLLS165G − JANUARY 1994 − REVISED MARCH 2006 Int ..
TL16C554IFN ,Quad UART with 16-Byte FIFOs SLLS165G − JANUARY 1994 − REVISED MARCH 2006 Int ..
TL16C554IFNG4 , ASYNCHRONOUS COMMUNICATIONS ELEMENT
TL16C554IFNR ,Quad UART with 16-Byte FIFOs SLLS165G − JANUARY 1994 − REVISED MARCH 2006 Int ..
TLV2763IDGS ,Dual 1.8-V, Micro-power, Rail-to-Rail, Single Supply Amplifier with Shutdownmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage, V ..
TLV2763IDGSR ,Dual 1.8-V, Micro-power, Rail-to-Rail, Single Supply Amplifier with ShutdownTLV2760, TLV2761, TLV2762, TLV2763, TLV2764, TLV2765 FAMILY OF 1.8 V MICROPOWER RAIL-TO-RAIL INPUT/ ..
TLV2764IPW ,Quad 1.8-V, Micro-power, Rail-to-Rail, Single Supply Amplifiermaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage, V ..
TLV2764IPWG4 ,Quad 1.8-V, Micro-power, Rail-to-Rail, Single Supply Amplifier 14-TSSOP -40 to 85TLV2760, TLV2761, TLV2762, TLV2763, TLV2764, TLV2765 FAMILY OF 1.8 V MICROPOWER RAIL-TO-RAIL INPUT/ ..
TLV2764IPWR ,Quad 1.8-V, Micro-power, Rail-to-Rail, Single Supply Amplifier.2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265TLV2760, TLV2761, TLV2762, TLV2763, TLV2764, TLV2765 ..
TLV2765 ,Quad 1.8-V, Micro-power, Rail-to-Rail, Single Supply Amplifier with Shutdownmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage, V ..
TL16C554AIFN-TL16C554AIFNR-TL16C554AIPN
Quad UART with 16-Byte FIFOs
TL16C554A, TL16C554AI
ASYNCHRONOUS-COMMUNICATIONS ELEMENT
SLLS509E − AUGUST 2001 − REVISED JUNE 2010
Integrated Asynchronous-Communications
Element Consists of Four Improved TL16C550C
ACEs Plus Steering Logic In FIFO Mode, Each ACE Transmitter and
Receiver Is Buffered With 16-Byte FIFO to
Reduce the Number of Interrupts to CPU In TL16C450 Mode, Hold and Shift
Registers Eliminate Need for Precise
Synchronization Between the CPU and
Serial Data Up to 16-MHz Clock Rate for up to 1-Mbaud
Operation with VCC = 3.3 V and 5 V Programmable Baud-Rate Generators
Which Allow Division of Any Input
Reference Clock by 1 to (216 �−�1) and
Generate an Internal 16 × Clock Adds or Deletes Standard Asynchronous
Communication Bits (Start, Stop, and
Parity) to or From the Serial-Data Stream Independently Controlled Transmit,
Receive, Line Status, and Data Set
Interrupts 5-V and 3.3-V Operation Fully Programmable Serial Interface
Characteristics:
− 5-, 6-, 7-, or 8-Bit Characters
− Even-, Odd-, or No-Parity Bit
− 1-, 1 1/2-, or 2-Stop Bit Generation
− Baud Generation (DC to 1-Mbit Per
Second) False Start Bit Detection Complete Status Reporting Capabilities Line Break Generation and Detection Internal Diagnostic Capabilities:
− Loopback Controls for Communications
Link Fault Isolation
− Break, Parity, Overrun, Framing Error
Simulation Fully Prioritized Interrupt System Controls Modem Control Functions (CTS, RTS, DSR,
DTR, RI, and DCD) 3-State Outputs Provide TTL Drive
Capabilities for Bidirectional Data Bus and
Control Bus Programmable Auto-RTS and Auto-CTS CTS Controls Transmitter in Auto-CTS
Mode, RCV FIFO Contents and Threshold Control
RTS in Auto-RTS Mode,
descriptionThe TL16C554A is an enhanced quadruple version of the TL16C550C asynchronous-communications element
(ACE). Each channel performs serial-to-parallel conversion on data characters received from peripheral
devices or modems and parallel-to-serial conversion on data characters transmitted by the CPU. The complete
status of each channel of the quadruple ACE can be read by the CPU at any time during operation. The
information obtained includes the type and condition of the operation performed and any error conditions
encountered.
The TL16C554A quadruple ACE can be placed in an alternate FIFO mode, which activates the internal FIFOs
to allow 16 bytes (plus three bits of error data per byte in the receiver FIFO) to be stored in both receive and
transmit modes. In the FIFO mode of operation, there is a selectable autoflow control feature that can
significantly reduce software overhead and increase system efficiency by automatically controlling serial-data
flow using RTS output and CTS input signals. All logic is on the chip to minimize system overhead and maximize
system efficiency. Two terminal functions allow signaling of direct-memory access (DMA) transfers. Each ACE
includes a programmable baud-rate generator that can divide the timing reference clock input by a divisor
between 1 and 216 −1.
The TL16C554A is available in a 68-pin plastic-leaded chip-carrier (PLCC) FN package, 64-pin plastic quad
flatpack (PQFP) PM package and in an 80-pin (TQFP) PN package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
