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TJA1043T
High-speed CAN transceiver
1. General descriptionThe TJA1043 is a high-speed CAN transceiver that provides an interface between a
Controller Area Network (CAN) protocol controller and the physical two-wire CAN bus.
The transceiver is designed for high-speed (up to 1 Mbit/s) CAN applications in the
automotive industry, providing differential transmit and receive capability to (a
microcontroller with) a CAN protocol controller.
The TJA1043 belongs to the third generation of high-speed CAN transceivers from NXP
Semiconductors, offering significant improvements over first- and second-generation
devices such as the TJA1041A. It offers improved ElectroMagnetic Compatibility (EMC)
and ElectroMagnetic Discharge (ESD) performance, very low power consumption, and
passive behavior when the supply voltage is turned off. Advanced features include:
Low-power management controls the power supply throughout the node while
supporting local and remote wake-up with wake-up source recognition
Several protection and diagnostic functions including bus line short-circuit detection
and battery connection detection
Can be interfaced directly to microcontrollers with supply voltages from 3Vto5V
These features make the TJA1043 the ideal choice for high speed CAN networks
containing nodes that need to be available all times, even when the internal VIO and VCC
supplies are switched off.
2. Features and benefits
2.1 General Fully ISO 11898-2 and ISO 11898-5 compliant Suitable for 12 V and 24 V systems Low ElectroMagnetic Emission (EME) and high ElectroMagnetic Immunity (EMI) VIO input allows for direct interfacing with 3 V and 5 V microcontrollers SPLIT voltage output for stabilizing the recessive bus level Listen-only mode for node diagnosis and failure containment Available in SO14 and HVSON14 packages Leadless HVSON14 package (3.0 mm 4.5 mm) with improved Automated Optical
Inspection (AOI) capability Dark green product (halogen free and Restriction of Hazardous Substances (RoHS)
compliant)
TJA1043
High-speed CAN transceiver
Rev. 3 — 24 April 2013 Product data sheet
NXP Semiconductors TJA1043
High-speed CAN transceiver
2.2 Low-power management Very low current Standby and Sleep modes, with local and remote wake-up Capability to power down the entire node while supporting local, remote and host
wake-up Wake-up source recognition Transceiver disengages from the bus (zero load) when VBAT absent Functional behavior predictable under all supply conditions
2.3 Protection and diagnosis (detection and signalling) High ESD handling capability on the bus pins Bus pins and VBAT protected against transients in automotive environments Transmit Data (TXD) dominant time-out function with diagnosis TXD-to-RXD short-circuit handler with diagnosis Thermal protection with diagnosis Undervoltage detection and recovery on pins VCC, VIO and VBAT Bus line short-circuit diagnosis Bus dominant clamping diagnosis Cold start diagnosis (first battery connection)
3. Quick reference data
4. Ordering information
Table 1. Quick reference dataVCC supply voltage 4.5 - 5.5 V
Vuvd(VCC) undervoltage detection voltage on pin VCC 33.5 4.3 V
ICC supply current Normal mode; bus dominant 30 48 65 mA
Normal or Listen-only mode; bus recessive 36 9 mA
Standby or Sleep mode 0 0.752 A
VESD electrostatic discharge voltage IEC 61000-4-2 at pins CANH and CANL 8- +8 kV
VCANH voltage on pin CANH no time limit; DC limiting value 58 - +58 V
VCANL voltage on pin CANL no time limit; DC limiting value 58 - +58 V
Tvj virtual junction temperature 40 - +150 C
Table 2. Ordering informationTJA1043T SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
TJA1043TK HVSON14 plastic, thermal enhanced very thin small outline package; no leads; terminals; body 3 4.5 0.85 mm
SOT1086-2
NXP Semiconductors TJA1043
High-speed CAN transceiver
5. Block diagramNXP Semiconductors TJA1043
High-speed CAN transceiver
6. Pinning information
6.1 Pinning
6.2 Pin description[1] For enhanced thermal and electrical performance, the exposed center pad of the HVSON14 package
should be soldered to board ground (and not to any other voltage level).
7. Functional descriptionThe TJA1043 is a stand-alone high-speed CAN transceiver with a number of operating
modes, fail-safe features and diagnostic features that offer enhanced system reliability
and advanced power management. The transceiver combines the functionality of the
Table 3. Pin descriptionTXD 1 transmit data input
GND[1] 2 ground supply
VCC 3 transceiver supply voltage
RXD 4 receive data output; reads out data from the bus lines
VIO 5 supply voltage for I/O level adaptor 6 enable control input
INH 7 inhibit output for switching external voltage regulators
ERR_N 8 error and power-on indication output (active LOW)
WAKE 9 local wake-up input
VBAT 10 battery supply voltage
SPLIT 11 common-mode stabilization output
CANL 12 LOW-level CAN bus line
CANH 13 HIGH-level CAN bus line
STB_N 14 standby control input (active LOW)
NXP Semiconductors TJA1043
High-speed CAN transceiverTJA1041A with improved EMC and ESD capability and quiescent current performance.
Improved slope control and high DC handling capability on the bus pins provide additional
application flexibility.
7.1 Operating modesThe TJA1043 supports five operating modes. Control pins STB_N and EN are used to
select the operating mode. Switching between modes allows access to a number of
diagnostics flags via pin ERR_N. Table 4 describes how to switch between modes.
Figure 4 illustrates the mode transitions when VCC, VIO and VBAT are valid.
[1] Setting the UVNOM flag will clear the WAKE flag.
[2] Setting the Wake flag will clear the UVNOM flag.
[3] A LOW-to-HIGH transition on pin STB_N will clear the UVNOM flag
[4] After the minimum hold time, in Go-to-Sleep mode, th(min), the transceiver will enter Sleep mode and pin
INH will be set floating.
Table 4. Operating mode selection
From Normal, Listen-only, Standby and Go-to-Sleep modesset X X X X Sleep mode floating
cleared set X HIGH X Standby mode HIGH
cleared X set LOW X Standby mode HIGH
cleared X cleared LOW LOW Standby mode HIGH
cleared X cleared LOW HIGH Go-to-Sleep mode[4] HIGH[4]
cleared cleared X HIGH LOW Listen-only mode HIGH
cleared cleared X HIGH HIGH Normal mode HIGH
From Sleep modeset X X X X Sleep mode floating
cleared set X HIGH X Standby mode HIGH
cleared X set LOW X Standby mode HIGH
cleared X cleared LOW X Sleep mode floating
cleared cleared X HIGH LOW Listen-only mode HIGH
cleared cleared X HIGH HIGH Normal mode HIGH
NXP Semiconductors TJA1043
High-speed CAN transceiver
7.1.1 Normal modeIn Normal mode, the transceiver can transmit and receive data via the bus lines CANH
and CANL (see Figure 1 for the block diagram). The differential receiver converts the
analog data on the bus lines into digital data which is output to pin RXD. The slope of the
output signals on the bus lines is controlled and optimized in a way that guarantees the
lowest possible EME. The bus pins are biased to 0.5VCC (via Ri). Pin INH is active, so
voltage regulators controlled by pin INH (see Figure 7) will be active too.
7.1.2 Listen-only modeIn Listen-only mode, the transceiver’s transmitter is disabled, effectively providing a
transceiver listen-only feature. The receiver will still convert the analog bus signal on
pins CANH and CANL into digital data, available for output on pin RXD. As in Normal
mode, the bus pins are biased at 0.5VCC and pin INH remains active.
NXP Semiconductors TJA1043
High-speed CAN transceiver
7.1.3 Standby modeStandby mode is the TJA1043’s first-level power saving mode, offering reduced current
consumption. In Standby mode, the transceiver is unable to transmit or receive data and
the low-power receiver is activated to monitor bus activity. The bus pins are biased at
ground level (via Ri). Pin INH is still active, so voltage regulators controlled by this pin will
also be active.
Pins RXD and ERR_N will reflect any active wake-up requests (provided that VIO and
VBAT are present).
7.1.4 Go-to-Sleep modeGo-to-Sleep mode is the controlled route for entering Sleep mode. In Go-to-Sleep mode,
the transceiver behaves as in Standby mode, with the addition that a go-to-sleep
command is issued to the transceiver. The transceiver will remain in Go-to-Sleep mode for
the minimum hold time (th(min)) before entering Sleep mode. The transceiver will not enter
Sleep mode if the state of pin STB_N or pin EN is changed or if the Wake flag is set
before th(min) has elapsed.
7.1.5 Sleep modeSleep mode is the TJA1043’s second-level power saving mode. Sleep mode is entered
via Go-to-Sleep mode, and also when the undervoltage detection time on either VCC or
VIO elapses before the relevant voltage level has recovered. In Sleep mode, the
transceiver behaves as described for Standby mode, with the exception that pin INH is set
floating. Voltage regulators controlled by this pin will be switched off, and the current into
pin VBAT will be reduced to a minimum. Pins STB_N, EN and the Wake flag can be used to
wake up a node from Sleep mode (see Table4).
7.2 Internal flagsThe TJA1043 makes use of seven internal flags for its fail-safe fallback mode control and
system diagnosis support. Five of these flags can be polled by the controller via pin
ERR_N. Which flag is available on pin ERR_N at any time depends on the active
operating mode and on a number of other conditions. Table 5 describes how to access
these flags.
Table 5. Accessing internal flags via pin ERR_NUVNOM no by setting the Pwon or Wake flags, by a LOW-to-HIGH transition on STB_N or
when both VIO and VBAT have
recovered.
UVBAT no when VBAT has recovered
Pwon in Listen-only mode (coming from Standby
mode, Go-to-Sleep mode, or Sleep mode)
on entering Normal mode
Wake in Standby mode, Go-to-Sleep mode, and Sleep mode (provided that VIO and VBAT
are present)
on entering Normal mode or by setting
the UVNOM flag
NXP Semiconductors TJA1043
High-speed CAN transceiver[1] Pin ERR_N is an active-LOW output, so a LOW-level indicates a set flag and a HIGH-level indicates a
cleared flag. Allow pin ERR_N to stabilize for at least 8 s after changing operating modes.
[2] Allow for a TXD dominant time of at least 4 s per dominant-recessive cycle.
7.2.1 UVNOM flagUVNOM is the VCC and VIO undervoltage detection flag. The flag is set when the voltage on
pin VCC drops below the VCC undervoltage detection voltage, Vuvd(VCC), for longer than the
undervoltage detection time, tdet(uv), or when the voltage on pin VIO drops below Vuvd(VIO)
for longer than tdet(uv). When the UVNOM flag is set, the transceiver enters Sleep mode to
save power and to ensure the bus is not disturbed. In Sleep mode the voltage regulators
connected to pin INH are disabled, avoiding any extra power consumption that might be
generated as a result of a short-circuit condition.
Any wake-up request, setting the Pwon flag or a LOW-to-HIGH transition on STB_N will
clear UVNOM and the timers, allowing the voltage regulators to be reactivated (at least until
UVNOM is set again). UVNOM will also be cleared if both VCC and VIO recover for longer
than the undervoltage recovery time, trec(uv). The transceiver will then switch to the
operating mode indicated by the logic levels on pins STB_N and EN (see Table 4).
7.2.2 UVBAT flagUVBAT is the VBAT undervoltage detection flag. This flag is set when the voltage on
pin VBAT drops below Vuvd(VBAT). When UVBAT is set, the transceiver will try to enter
Standby mode to save power and will disengage from the bus (zero load). UVBAT is
cleared when the voltage on pin VBAT recovers. The transceiver will then switch to the
operating mode indicated by the logic levels on pins STB_N and EN (see Table 4).
7.2.3 Pwon flagPwon is the VBAT power-on flag. This flag is set when the voltage on pin VBAT recovers
after previously dropping below Vuvd(VBAT) (usually because the battery was
disconnected). Setting the Pwon flag clears the UVNOM flag and timers. The Wake and
Wake-up source flags are set to ensure consistent system power-up under all supply
conditions. In Listen-only mode the Pwon flag can be polled via pin ERR_N (see Table 5).
The flag is cleared when the transceiver enters Normal mode.
7.2.4 Wake flagThe Wake flag is set when the transceiver detects a local or remote wake-up request. A
local wake-up request is detected when the logic level on pin WAKE changes, and the
new level remains stable for at least twake. A remote wake-up request is triggered by two
bus dominant states of at least twake(busdom), with the first dominant state followed by a
Wake-up
source
in Normal mode (before the fourth
dominant-to-recessive edge on pin TXD[2])
on leaving Normal mode
Bus failure in Normal mode (after the fourth
dominant-to-recessive edge on pin TXD[2]
on re-entering Normal mode or by
setting the Pwon flag
Local failure in Listen-only mode (coming from Normal
mode)
on entering Normal mode or when RXD
is dominant while TXD is recessive
(provided that all local failures are
resolved) or by setting the Pwon flag
Table 5. Accessing internal flags via pin ERR_N …continued
NXP Semiconductors TJA1043
High-speed CAN transceiverrecessive state of at least twake(busrec) (provided the complete
dominant-recessive-dominant pattern is completed within tto(wake)bus). The Wake flag can
be set in Standby mode, Go-to-Sleep mode or Sleep mode. Setting the Wake flag clears
the UVNOM flag and timers. Once set, the Wake flag status is immediately available on
pins ERR_N and RXD (provided VIO and VBAT are present). This flag is also set at
power-on and cleared when the UVNOM flag is set or the transceiver enters Normal mode.
7.2.5 Wake-up source flagWake-up source recognition is provided via the Wake-up source flag, which is set when
the Wake flag is set by a local wake-up request via the WAKE pin. The Wake-up source
flag can be polled via the ERR_N pin in Normal mode (see Table 5). This flag is also set at
power-on and cleared when the transceiver leaves Normal mode.
7.2.6 Bus failure flagThe Bus failure flag is set if the transceiver detects a bus line short-circuit condition to
VBAT, VCC or GND during four consecutive dominant-recessive cycles on pin TXD, while
trying to drive the bus lines dominant. The Bus failure flag can be polled via the ERR_N
pin in Normal mode (see Table 5). This flag is cleared at power-on or when the transceiver
re-enters Normal mode.
7.2.7 Local failure flagIn Normal and Listen-only modes, the transceiver can distinguish four different local
failure events, any of which will cause the Local failure flag to be set. The four local failure
events are: TXD dominant clamping, TXD-to-RXD short circuit, bus dominant clamping
and an overtemperature event. The nature and detection of these local failures is
described in Section 7.3. The Local failure flag can be polled via the ERR_N pin in
Listen-only mode (see Table 5). This flag is cleared at power-on, when entering Normal
mode or when RXD is dominant while TXD is recessive, provided that all local failures
have been resolved.
7.3 Local failuresThe TJA1043 can detect four different local failure conditions. Any of these failures will set
the Local failure flag, and in most cases the transmitter of the transceiver will be disabled.
7.3.1 TXD dominant clamping detectionA permanent LOW level on pin TXD (due to a hardware or software application failure)
would drive the CAN bus into a permanent dominant state, blocking all network
communications. The TXD dominant time-out function prevents such a network lock-up by
disabling the transmitter if pin TXD remains LOW for longer than the TXD dominant
time-out time tto(dom)TXD. The tto(dom)TXD timer defines the minimum possible bit rate of kbit/s. The transmitter remains disabled until the Local failure flag has been cleared.
7.3.2 TXD-to-RXD short-circuit detectionA short-circuit between pins RXD and TXD would lock the bus in a permanent dominant
state once it had been driven dominant, because the low-side driver of RXD is typically
stronger than the high-side driver of the controller connected to TXD. TXD-to-RXD
short-circuit detection prevents such a network lock-up by disabling the transmitter. The
transmitter remains disabled until the Local failure flag has been cleared.
NXP Semiconductors TJA1043
High-speed CAN transceiver
7.3.3 Bus dominant clamping detectionA CAN bus short circuit (to VBAT, VCC or GND) or a failure in one of the other network
nodes could result in a differential voltage on the bus high enough to represent a bus
dominant state. Because a node will not start transmission if the bus is dominant, the
normal bus failure detection will not detect this failure, but the bus dominant clamping
detection will. The Local failure flag is set if the dominant state on the bus persists for
longer than tto(dom)bus. By checking this flag, the controller can determine if a clamped bus
is blocking network communications. There is no need to disable the transmitter. Note that
the Local failure flag does not retain a bus dominant clamping failure, and is released as
soon as the bus returns to recessive state.
7.3.4 Overtemperature detectionIf the junction temperature becomes excessive, the transmitter will shut down in time to
protect the output drivers from overheating without compromising the maximum operating
temperature. The transmitter will remain disabled until the Local failure flag has been
cleared.
7.4 SPLIT pinUsing the SPLIT pin on the TJA1043 in conjunction with a split termination network (see
Figure 5 and Figure 7) can help to stabilize the recessive voltage level on the bus. This
will reduce EME in networks with DC leakage to ground (e.g. from deactivated nodes with
poor bus leakage performance). In Normal and Listen-only modes, pin SPLIT delivers a
DC output voltage of 0.5VCC. In Standby, Go-to-Sleep and Sleep modes, pin SPLIT is
floating.
7.5 VIO supply pinPin VIO should be connected to the microcontroller supply voltage (see Figure 7). This will
cause the signal levels of pins TXD, RXD, STB_N, EN and ERR_N to be adjusted to the
I/O levels of the microcontroller, facilitating direct interfacing without the need for glue
logic.
NXP Semiconductors TJA1043
High-speed CAN transceiver
7.6 WAKE pinA local wake-up event is triggered by a LOW-to-HIGH or HIGH-to-LOW transition on the
WAKE pin, allowing for maximum flexibility when designing a local wake-up circuit.To
minimize current consumption, the internal bias voltage will follow the logic state on the
pin after a delay of twake. A HIGH level on pin WAKE is followed by an internal pull-up to
VBAT. A LOW level on pin WAKE is followed by an internal pull-down towards GND. In
applications that don’t make use of the local wake-up facility, it is recommended that the
WAKE pin be connected to VBAT or GND to ensure optimal EMI performance.
NXP Semiconductors TJA1043
High-speed CAN transceiver
8. Limiting values[1] Verified by an external test house to ensure pins CANH, CANL, SPLIT and VBAT can withstand ISO 7637 part 3 automotive transient test
pulses 1, 2a, 3a and 3b.
[2] IEC 61000-4-2 (150 pF, 330 ); direct coupling.
[3] ESD performance of pins CANH and CANL according to IEC 61000-4-2 (150 pF, 330 ) has been verified by an external test house.
The result is equal to or better than 8 kV (unaided).
[4] Human Body Model (HBM): according to AEC-Q100-002 (100 pF, 1.5 k).
[5] Machine Model (MM): according to AEC-Q100-003 (200 pF, 0.75 H, 10 ).
[6] Charged Device Model (CDM): according to AEC-Q100-011 (field Induced charge; 4 pF); grade C3B.
[7] In accordance with IEC 60747-1. An alternative definition of virtual junction temperature is: Tvj =Tamb+P Rth(vj-a), where Rth(vj-a) is a
fixed value to be used for the calculation of Tvj. The rating for Tvj limits the allowable combinations of power dissipation (P) and ambient
temperature (Tamb).
9. Thermal characteristics
Table 6. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).
VBAT battery supply voltage no time limit 0.3 +58 V
load dump - 58 V voltage on pin x no time limit; DC value
on pins CANH, CANL and SPLIT 58 +58 V
on pins INH and WAKE 0.3 +58 V
on pins VCC, VIO, TXD, RXD, STB_N, EN,
ERR_N 0.3 +7 V
IWAKE current on pin WAKE DC value - 15 mA
Vtrt transient voltage on pins CANH, CANL, SPLIT and VBAT [1] 200 +200 V
VESD electrostatic discharge
voltage
IEC 61000-4-2 [2]
at pins CANH and CANL [3] 8+8 kV
HBM [4]
at pins CANH and CANL 8+8 kV
at any other pin 4+4 kV [5]
at any pin 300 +300 V
CDM [6]
at corner pins 750 +750 V
at any pin 500 +500 V
Tvj virtual junction temperature [7] 40 +150 C
Tstg storage temperature 55 +150 C
Table 7. Thermal characteristicsValue determined for free convection conditions on a JEDEC 2S2P board.
Rth(vj-a) thermal resistance from virtual junction to ambient SO14 package; in free air 68 K/W
HVSON14 package; in free air 44 K/W
NXP Semiconductors TJA1043
High-speed CAN transceiver
10. Static characteristicsTable 8. Static characteristicsVCC= 4.5Vto 5.5 V; VIO = 2.8 V to VCC; VBAT =4.5 Vto40V; RL =60 ; Tvj= 40 Cto+150 C; unless otherwise
specified; all voltages are defined with respect to ground; positive currents flow into the device [1]
Supply pin VCCVCC supply voltage 4.5 - 5.5 V
Vuvd(VCC) undervoltage detection
voltage on pin VCC
VBAT> 4.5V 3 3.5 4.3 V
ICC supply current Normal mode; VTXD=0 V (dominant) 30 48 65 mA
Normal or Listen-only mode;
VTXD =VIO (recessive) 9 mA
Standby or Sleep mode; VBAT > VCC 00.75 2 A
I/O level adapter supply; pin VIOVIO supply voltage on pin VIO 2.8 - 5.5 V
Vuvd(VIO) undervoltage detection
voltage on pin VIO
VBAT or VCC > 4.5V 0.8 1.8 2.5 V
IIO supply current on pin VIO Normal mode; VTXD=0 V (dominant) - 150 500 A
Normal or Listen-only mode;
VTXD =VIO (recessive) 4 A
Standby or Sleep mode 0 1 4 A
Supply pin VBATVBAT battery supply voltage 4.5 - 40 V
Vuvd(VBAT) undervoltage detection
voltage on pin VBAT
33.5 4.3 V
IBAT battery supply current Normal or Listen-only mode 15 40 70 A
Standby mode; VCC >4.5V
VINH =VWAKE =VBAT
518 30 A
Sleep mode; VINH =VCC =VIO =0V;
VWAKE =VBAT
518 30 A
CAN transmit data input; pin TXDVIH HIGH-level input voltage 0.7VIO -VIO +0.3V
VIL LOW-level input voltage 0.3 - +0.3VIO V
IIH HIGH-level input current VTXD =VIO 50 +5 A
IIL LOW-level input current Normal mode; VTXD = 0V 300 200 30 A input capacitance not tested - 5 10 pF
CAN receive data output; pin RXDIOH HIGH-level output current VRXD =VIO 0.4 V; VIO =VCC 12 60 mA
IOL LOW-level output current VRXD= 0.4 V; VTXD =VIO;
bus dominant 14 mA
Standby and enable control inputs; pins STB_N and ENVIH HIGH-level input voltage 0.7VIO -VIO +0.3V
VIL LOW-level input voltage 0.3 - 0.3VIO V
IIH HIGH-level input current VSTB_N =VEN =0.7VIO 14 10 A
NXP Semiconductors TJA1043
High-speed CAN transceiverIIL LOW-level input current VSTB_N =VEN =0V 10 +1 A
Error and power-on indication output; pin ERR_NIOH HIGH-level output current VERR_N =VIO 0.4 V; VIO =VCC 50 20 4 A
IOL LOW-level output current VERR_N= 0.4V 0.1 0.5 2 mA
Local wake-up input; pin WAKEIIH HIGH-level input current VWAKE =VBAT 1.9V 10 5 1 A
IIL LOW-level input current VWAKE =VBAT 3.1V 1 5 10 A
Vth threshold voltage VSTB_N =0V VBAT 3VBAT 2.5 VBAT 2V
Inhibit output; pin INHVH HIGH-level voltage drop IINH= 0.18 mA 0 0.25 0.8 V leakage current Sleep mode 20 +2 A
Bus lines; pins CANH and CANLVO(dom) dominant output voltage VTXD =0V; t< tto(dom)TXD
pin CANH 2.75 3.5 4.5 V
pin CANL 0.5 1.5 2.25 V
Vdom(TX)sym transmitter dominant
voltage symmetry
Vdom(TX)sym = VCC VCANH VCANL 400 - +400 mV
VO(dif)bus bus differential output
voltage
VTXD =0V; VCC= 4.75 V to 5.25 V;
1.5 - 3.0 V
VTXD =VIO; recessive; no load 50 - +50 mV
VO(rec) recessive output voltage Normal or Listen-only mode;
VTXD =VIO; no load
20.5VCC 3V
Standby or Sleep mode; no load 0.1 0 +0.1 V
IO(sc) short-circuit output current VTXD=0 V (dominant); VCC =5V
pin CANH; VCANH =0V 100 70 40 mA
pin CANL; VCANL=40V 40 70 100 mA
IO(rec) recessive output current 27V< VCAN <32V 3- +3 mA
Vth(RX)dif differential receiver
threshold voltage
Vcm(CAN)= 30Vto +30V [2]
Normal or Listen-only mode 0.5 0.7 0.9 V
Standby or Sleep mode 0.4 0.7 1.15 V
Vhys(RX)dif differential receiver
hysteresis voltage
Normal or Listen-only mode
Vcm(CAN)= 30Vto +30V
[2] 50 120 400 mV
ILI input leakage current VCC =0V; VCANH =VCANL=5V 100 170 250 A
VBAT =0V; VCANH =VCANL =5V 2- +2 A input resistance 9 15 28 k
Ri input resistance deviation between VCANH and VCANL 30 +3 %
Ri(dif) differential input resistance 19 30 52 k
Ci(cm) common-mode input
capacitance
VTXD =VCC [3]- - 20 pF
Ci(dif) differential input
capacitance
VTXD =VCC [3]- - 10 pF
Table 8. Static characteristics …continued
VCC= 4.5Vto 5.5 V; VIO = 2.8 V to VCC; VBAT =4.5 Vto40V; RL =60 ; Tvj= 40 Cto+150 C; unless otherwise
specified; all voltages are defined with respect to ground; positive currents flow into the device [1].
