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TJA1041T
High-speed CAN transceiver with standby and sleep mode
General descriptionThe TJA1041 provides an advanced interface between the protocol controller and the
physical busina Controller Area Network (CAN) node. The TJA1041is primarily intended
for automotive high-speed CAN applications (up to 1 Mbit/s). The transceiver provides
differential transmit capability to the bus and differential receive capability to the CAN
controller. The TJA1041 is fully compatible to the ISO 11898 standard, and offers
excellent ElectroMagnetic Compatibility (EMC) performance, very low power
consumption, and passive behavior when supply voltage is off. The advanced features
include: Low-power management, supporting local and remote wake-up with wake-up source
recognition and the capability to control the power supply in the rest of the node Several protection and diagnosis functions including short circuitsof the bus lines and
ﬁrst battery connection Automatic adaptation of the I/O-levels, in line with the supply voltage of the controller Features
2.1 Optimized for in-vehicle high speed communication Fully compatible with the ISO 11898 standard Communication speed up to 1 Mbit/s Very low ElectroMagnetic Emission (EME) Differential receiver with wide common-mode range, offering high ElectroMagnetic
Immunity (EMI) Passive behavior when supply voltage is off Automatic I/O-level adaptation to the host controller supply voltage Recessive bus DC voltage stabilization for further improvement of EME behavior Listen-only mode for node diagnosis and failure containment Allows implementation of large networks (more than 110 nodes)
2.2 Low-power management Very low-current in Standby and Sleep mode, with local and remote wake-up Capability to power-down the entire node, still allowing local and remote wake-up Wake-up source recognition
TJA1041
High speed CAN transceiver
Rev. 06 — 5 December 2007 Product data sheet
NXP Semiconductors TJA1041
High speed CAN transceiver
2.3 Protection and diagnosis (detection and signalling) TXD dominant clamping handler with diagnosis RXD recessive clamping handler with diagnosis TXD-to-RXD short-circuit handler with diagnosis Overtemperature protection with diagnosis Undervoltage detection on pins VCC, VI/O and VBAT Automotive environment transient protected bus pins and pin VBAT Short-circuit proof bus pins and pin SPLIT (to battery and to ground) Bus line short-circuit diagnosis Bus dominant clamping diagnosis Cold start diagnosis (ﬁrst battery connection) Quick reference data
[1] Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor (6 kV level with pin GND connected to ground). Ordering information
Table 1. Quick reference data
VCC DC voltage on pin VCC operating range 4.75 - 5.25 V
VI/O DC voltage on pin VI/O operating range 2.8 - 5.25 V
VBAT DC voltage on pin VBAT operating range 5 - 27 V
IBAT VBAT input current VBAT = 12 V 10 - 30 μA
VCANH DC voltage on pin CANH 0 V < VCC < 5.25 V; no time limit −27 - +40 V
VCANL DC voltage on pin CANL 0 V < VCC < 5.25 V; no time limit −27 - +40 V
VSPLIT DC voltage on pin SPLIT 0 V < VCC < 5.25 V; no time limit −27 - +40 V
Vesd electrostatic discharge voltage Human Body Model (HBM) [1]
pins CANH, CANL and SPLIT −6 - +6 kV
pins TXD, RXD, VI/O and STB −3 - +3 kV
all other pins −4 - +4 kV
tPD(TXD-RXD) propagation delay TXD to RXD VSTB = 0 V 40 - 255 ns
Tvj virtual junction temperature −40 - +150 °C
Table 2. Ordering information
TJA1041T SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
TJA1041U - bare die; 1930 × 3200 × 380 μm-
NXP Semiconductors TJA1041
High speed CAN transceiver Block diagram
NXP Semiconductors TJA1041
High speed CAN transceiver Pinning information
6.1 Pinning
6.2 Pin description
Table 3. Pin description
TXD 1 transmit data input
GND 2 ground
VCC 3 transceiver supply voltage input
RXD 4 receive data output; reads out data from the bus lines
VI/O 5 I/O-level adapter voltage input 6 enable control input
INH 7 inhibit output for switching external voltage regulators
ERR 8 error and power-on indication output (active LOW)
WAKE 9 local wake-up input
VBAT 10 battery voltage input
SPLIT 11 common-mode stabilization output
CANL 12 LOW-level CAN bus line
CANH 13 HIGH-level CAN bus line
STB 14 standby control input (active LOW)
NXP Semiconductors TJA1041
High speed CAN transceiver Functional description
The primary function of a CAN transceiver is to provide the CAN physical layer as
described in the ISO 11898 standard. In the TJA1041 this primary function is
complemented with a number of operating modes, fail-safe features and diagnosis
features, which offer enhanced system reliability and advanced power management
functionality.
7.1 Operating modes
The TJA1041 can be operated in ﬁve modes, each with speciﬁc features. Control pins
STB and EN select the operating mode. Changing between modes also gives accesstoa
number of diagnostics ﬂags, available via pin ERR. The following sections describe the
ﬁve operating modes.T able 4 shows the conditions for selecting these modes. Figure3
illustrates the mode transitions when VCC, VI/O and VBAT are present.
[1] X = don’t care.
[2] Setting the pwon ﬂag or the wake-up ﬂag will clear the UVNOM ﬂag.
[3] The transceiver directly enters Sleep mode and pin INH is set ﬂoating when the UVNOM ﬂag is set (so after
the undervoltage detection time on either VCC or VI/O has elapsed before that voltage level has recovered).
[4] When go-to-sleep command mode is selected for longer than the minimum hold time of the go-to-sleep
command, the transceiver will enter Sleep mode and pin INH is set ﬂoating.
[5] On entering normal mode the pwon ﬂag and the wake-up ﬂag will be cleared.
Table 4. Operating mode selection[1] X set X X[2] Sleep mode[3] ﬂoating
cleared set one or both set Standby mode H
both cleared no change from Sleep mode ﬂoating
Standby mode from any
other mode L cleared cleared one or both set Standby mode H
both cleared no change from Sleep mode ﬂoating
Standby mode from any
other mode H cleared cleared one or both set Standby mode H
both cleared no change from Sleep mode ﬂoating
go-to-sleep command mode
from any other mode[4] H[4] L cleared cleared X pwon/listen-only mode H H cleared cleared X normal mode[5] H
NXP Semiconductors TJA1041
High speed CAN transceiver
7.1.1 Normal mode
Normal mode is the mode for normal bidirectional CAN communication. The receiver will
convert the differential analog bus signal on pins CANH and CANL into digital data,
available for output to pin RXD. The transmitter will convert digital data on pin TXD into a
differential analog signal, available for output to the bus pins. The bus pins are biased at
0.5VCC (via Ri(cm)). Pin INH is active, so voltage regulators controlled by pin INH (see
Figure 4) will be active too.
7.1.2 Pwon/listen-only mode
In pwon/listen-only mode the transmitter of the transceiver is disabled, effectively
providing a transceiver listen-only behavior. The receiver will still convert the analog bus
signal on pins CANH and CANL into digital data, available for output to pin RXD. As in
normal mode the bus pins are biased at 0.5VCC, and pin INH remains active.
NXP Semiconductors TJA1041
High speed CAN transceiver
7.1.3 Standby mode
The Standby modeis the ﬁrst-level power saving modeof the transceiver, offering reduced
current consumption. In Standby mode the transceiver is not able to transmit or receive
data and the low-power receiver is activated to monitor bus activity. The bus pins are
biased at ground level (via Ri(cm)). Pin INH is still active, so voltage regulators controlled
by this pin INH will be active too.
Pins RXD and ERR will reﬂect any wake-up requests (provided that VI/O and VCC are
present).
7.1.4 Go-to-sleep command mode
The go-to-sleep command mode is the controlled route for entering Sleep mode. In
go-to-sleep command mode the transceiver behaves as if in Standby mode, plus a
go-to-sleep command is issued to the transceiver. After remaining in go-to-sleep
command modefor the minimum hold time (th(min)), the transceiver will enter Sleep mode.
The transceiver will not enter the Sleep modeif the stateof pins STBor ENis changedor
the UVBAT, pwon or wake-up ﬂag is set before th(min) has expired.
7.1.5 Sleep mode
The Sleep modeis the second-level power saving modeof the transceiver. Sleep modeis
entered via the go-to-sleep command mode, and also when the undervoltage detection
timeon either VCCor VI/O elapses before that voltage level has recovered.In Sleep mode
the transceiver still behaves as described for Standby mode, but now pin INH is set
ﬂoating. Voltage regulators controlled by pin INH will be switched off, and the current into
pin VBATis reducedtoa minimum. Wakingupa node from Sleep modeis possible via the
wake-up ﬂag and (as long as the UVNOM ﬂag is not set) via pin STB.
7.2 Internal ﬂags
The TJA1041 makes use of seven internal ﬂags for its fail-safe fallback mode control and
system diagnosis support. Table4 shows the relation between ﬂags and operating modes the transceiver. Fiveof the internal ﬂags canbe made availableto the controller via pin
ERR. Table 5 shows the details on how to access these ﬂags. The following sections
describe the seven internal ﬂags.
Table 5. Accessing internal ﬂags via pin ERR
UVNOM no by setting the pwon or wake-up
ﬂag
UVBAT no when VBAT has recovered
pwon in pwon/listen-only mode (coming from
Standby mode, go-to-sleep command mode,
or Sleep mode)
on entering normal mode
wake-up in Standby mode, go-to-sleep command
mode, and Sleep mode (provided that VI/O
and VCC are present)
on entering normal mode, or by
setting the pwon or UVNOM ﬂag
NXP Semiconductors TJA1041
High speed CAN transceiver
[1] Pin ERRisan active-LOW output,soa LOW level indicatesaset ﬂag anda HIGH level indicatesa cleared
ﬂag. Allow pin ERR to stabilize for at least 8 μs after changing operating modes.
[2] Allow for a TXD dominant time of at least 4 μs per dominant-recessive cycle.
7.2.1 UVNOM ﬂag
UVNOM is the VCC and VI/O undervoltage detection ﬂag. The ﬂag is set when the voltage
on pin VCC drops below VCC(sleep) for longer than tUV(VCC) or when the voltage on pin VI/O
drops below VI/O(sleep)for longer than tUV(VI/O). When the UVNOM ﬂagis set, the transceiver
will enter Sleep mode to save power and not disturb the bus. In Sleep mode the voltage
regulators connected to pin INH are disabled, avoiding the extra power consumption in
case of a short-circuit condition. After a waiting time (ﬁxed by the same timers used for
setting UVNOM) any wake-up request or setting of the pwon ﬂag will clear UVNOM and the
timers, allowing the voltage regulators to be reactivated at least until UVNOM is set again.
7.2.2 UVBAT ﬂag
UVBATis the VBAT undervoltage detection ﬂag. The ﬂagis set when the voltageon pin VBAT
drops below VBAT(stb). When UVBATis set, the transceiver willtryto enter Standby modeto
save power and not disturb the bus. UVBAT is cleared when the voltage on pin VBAT has
recovered. The transceiver will then returnto the operating mode determinedby the logic
state of pins STB and EN.
7.2.3 Pwon ﬂag
Pwon is the VBAT power-on ﬂag. This ﬂag is set when the voltage on pin VBAT has
recovered after it dropped below VBAT(pwon), particularly after the transceiver was
disconnected from the battery. By setting the pwon ﬂag, the UVNOM ﬂag and timers are
cleared and the transceiver cannot enter Sleep mode. This ensures that any voltage
regulator connectedto pin INHis activated when the nodeis reconnectedto the battery.In
pwon/listen-only mode the pwon ﬂag can be made available on pin ERR. The ﬂag is
cleared when the transceiver enters normal mode.
7.2.4 Wake-up ﬂag
The wake-up ﬂagis set when the transceiver detectsa localora remote wake-up request.
A local wake-up request is detected when a logic state change on pin WAKE remains
stable for at least twake. A remote wake-up request is detected when the bus remains in
dominant state for at least tBUS. The wake-up ﬂag can only be set in Standby mode,
go-to-sleep command mode or Sleep mode. Setting of the ﬂag is blocked during the
UVNOM ﬂag waiting time. By setting the wake-up ﬂag, the UVNOM ﬂag and timers are
wake-up
source normal mode (beforethe fourthdominantto
recessive edge on pin TXD[2]
on leaving normal mode, or by
setting the pwon ﬂag
bus failure in normal mode (after the fourth dominant to
recessive edge on pin TXD[2] on re-entering normal mode
local failure in pwon/listen-only mode (coming from
normal mode)
on entering normal mode or when
RXD is dominant while TXD is
recessive (provided that all local
failures are resolved)
Table 5. Accessing internal ﬂags via pin ERR …continued
NXP Semiconductors TJA1041
High speed CAN transceiver
cleared. The wake-up ﬂag is immediately available on pins ERR and RXD (provided that
VI/O and VCC are present). The ﬂagis clearedat power-on,or when the UVNOM ﬂagis set
or the transceiver enters normal mode.
7.2.5 Wake-up source ﬂag
Wake-up source recognition is provided via the wake-up source ﬂag, which is set when
the wake-up ﬂagis setbya local wake-up request via pin WAKE. The wake-up source ﬂag
can only be set after the pwon ﬂag is cleared. In normal mode the wake-up source ﬂag
can be made available on pin ERR. The ﬂag is cleared at power-on or when the
transceiver leaves normal mode.
7.2.6 Bus failure ﬂag
The bus failure ﬂag is set if the transceiver detects a bus line short-circuit condition to
VBAT, VCC or GND during four consecutive dominant-recessive cycles on pin TXD, when
trying to drive the bus lines dominant. In normal mode the bus failure ﬂag can be made
available on pin ERR. The ﬂag is cleared when the transceiver re-enters normal mode.
7.2.7 Local failure ﬂag normal modeor pwon/listen-only mode the transceiver can recognize ﬁve different local
failures, and will combine them into one local failure ﬂag. The ﬁve local failures are: TXD
dominant clamping, RXD recessive clamping, a TXD-to-RXD short circuit, bus dominant
clamping, and overtemperature. The nature and detection of these local failures is
describedin Section 7.3 “Local failures”.In pwon/listen-only mode the local failure ﬂag can
be made available on pin ERR. The ﬂag is cleared when entering normal mode or when
RXD is dominant while TXD is recessive, provided that all local failures are resolved.
7.3 Local failures
The TJA1041 can detect ﬁve different local failure conditions. Anyof these failures will set
the local failure ﬂag, and in most cases the transmitter of the transceiver will be disabled.
The following sections give the details.
7.3.1 TXD dominant clamping detection
A permanent LOW level on pin TXD (due to a hardware or software application failure)
would drive the CAN bus into a permanent dominant state, blocking all network
communication. The TXD dominant time-out function prevents such a network lock-up by
disabling the transmitter of the transceiver if pin TXD remains at a LOW level for longer
than the TXD dominant time-out tdom(TXD). The tdom(TXD) timer deﬁnes the minimum
possible bit rate of 40 kbit/s. The transmitter remains disabled until the local failure ﬂag is
cleared.
7.3.2 RXD recessive clamping detection
An RXD pin clamped to HIGH level will prevent the controller connected to this pin from
recognizinga bus dominant state. So the controller can start messagesat any time, which likelyto disturball bus communication. RXD recessive clamping detection prevents this
effectby disabling the transmitter when the busisin dominant state without RXD reﬂecting
this. The transmitter remains disabled until the local failure ﬂag is cleared.
NXP Semiconductors TJA1041
High speed CAN transceiver
7.3.3 TXD-to-RXD short-circuit detection
A short-circuit between pins RXD and TXD would keep the bus in a permanent dominant
state once the bus is driven dominant, because the low-side driver of RXD is typically
stronger than the high-side driver of the controller connected to TXD. The TXD-to-RXD
short-circuit detection prevents such a network lock-up by disabling the transmitter. The
transmitter remains disabled until the local failure ﬂag is cleared.
7.3.4 Bus dominant clamping detection
A CAN bus short circuit (to VBAT, VCC or GND) or a failure in one of the other network
nodes could result in a differential voltage on the bus high enough to represent a bus
dominant state. Because a node will not start transmission if the bus is dominant, the
normal bus failure detection will not detect this failure, but the bus dominant clamping
detection will. The local failure ﬂag is set if the dominant state on the bus persists for
longer than tdom(bus).By checking this ﬂag, the controller can determineifa clamped busis
blocking network communication. There is no need to disable the transmitter. Note that
the local failure ﬂag does not retain a bus dominant clamping failure, and is released as
soon as the bus returns to recessive state.
7.3.5 Overtemperature detection protect the output driversof the transceiver against overheating, the transmitter willbe
disabled if the virtual junction temperature exceeds the shutdown junction temperature
Tj(sd). The transmitter remains disabled until the local failure ﬂag is cleared.
7.4 Recessive bus voltage stabilization
In recessive state the output impedance of transceivers is relatively high. In a partially
powered network (supply voltageisoffin someof the nodes) any deactivated transceiver
with a signiﬁcant leakage current is likely to load the recessive bus to ground. This will
causea common-mode voltage step each time transmission starts, resultingin increased
EME. Using pin SPLITof the TJA1041in combination with split termination (see Figure5)
will reduce this step effect.In normal mode and pwon/listen-only mode pin SPLIT provides stabilized 0.5VCC DC voltage.In Standby mode, go-to-sleep command mode and Sleep
mode, pin SPLIT is set ﬂoating.
7.5 I/O level adapter
The TJA1041 is equipped with a built-in I/O-level adapter. By using the supply voltage of
the controller (to be supplied at pin VI/O) the level adapter ratio-metrically scales the
I/O-levels of the transceiver. For pins TXD, STB and EN the digital input threshold level is
adjusted, and for pins RXD and ERR the HIGH-level output voltage is adjusted. This
allows the transceivertobe directly interfaced with controllerson supply voltages between
2.8 V and 5.25 V, without the need for glue logic.
7.6 Pin WAKE
Pin WAKE of the TJA1041 allows local wake-up triggering by a LOW-to-HIGH state
change as well as a HIGH-to-LOW state change. This gives maximum ﬂexibility when
designinga local wake-up circuit.To keep current consumptionata minimum, aftera twake
delay the internal bias voltage of pin WAKE will follow the logic state of this pin. A HIGH
levelon pin WAKEis followedbyan internal pull-upto VBAT.A LOW levelon pin WAKEis
NXP Semiconductors TJA1041
High speed CAN transceiver
followed by an internal pull-down towards GND. T o ensure EMI performance in
applications not using local wake-up it is recommended to connect pin WAKE to pin VBAT
or to pin GND. Limiting values
[1] Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor (6 kV level with pin GND connected to ground).
[2] Equivalent to discharging a 200 pF capacitor via a 0.75 μH series inductor and a 10 Ω series resistor.
[3] Junction temperaturein accordance with IEC 60747-1.An alternative deﬁnitionis:Tvj =Tamb +P× Rth(vj-amb), where Rth(vj-amb) isaﬁxed
value. The rating for Tvj limits the allowable combinations of power dissipation (P) and ambient temperature (Tamb).
Table 6. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
VCC DC voltage on pin VCC no time limit −0.3 +6 V
operating range 4.75 5.25 V
VI/O DC voltage on pin VI/O no time limit −0.3 +6 V
operating range 2.8 5.25 V
VBAT DC voltage on pin VBAT no time limit −0.3 +40 V
operating range 5 27 V
load dump - 40 V
VTXD DC voltage on pin TXD −0.3 VI/O + 0.3 V
VRXD DC voltage on pin RXD −0.3 VI/O + 0.3 V
VSTB DC voltage on pin STB −0.3 VI/O + 0.3 V
VEN DC voltage on pin EN −0.3 VI/O + 0.3 V
VERR DC voltage on pin ERR −0.3 VI/O + 0.3 V
VINH DC voltage on pin INH −0.3 VBAT+ 0.3 V
VWAKE DC voltage on pin WAKE −0.3 VBAT+ 0.3 V
IWAKE DC current on pin WAKE - −15 mA
VCANH DC voltage on pin CANH 0V< VCC< 5.25V;no time limit −27 +40 V
VCANL DC voltage on pin CANL 0V< VCC< 5.25V;no time limit −27 +40 V
VSPLIT DC voltage on pin SPLIT 0V< VCC< 5.25V;no time limit −27 +40 V
Vtrt transient voltages on pins CANH,
CANL, SPLIT and VBAT
according to ISO 7637; see
Figure6
−200 +200 V
Vesd electrostatic discharge voltage Human Body Model (HBM) [1]
pins CANH, CANL and SPLIT −6+6 kV
pins TXD, RXD, VI/O and STB −3+3 kV
all other pins −4+4 kV
Machine Model (MM) [2] −200 +200 V
Tvj virtual junction temperature [3] −40 +150 °C
Tstg storage temperature −55 +150 °C
NXP Semiconductors TJA1041
High speed CAN transceiver Thermal characteristics
10. Characteristics
Table 7. Thermal characteristics
Rth(j-a) thermal resistance from junction
to ambient
SO14 package; in
free air
120 K/W
Rth(j-s) thermal resistance from junction
to substrate
bare die; in free air 40 K/W
Table 8. Characteristics
VCC = 4.75 V to 5.25 V; VI/O = 2.8 V to VCC; VBAT = 5 V to 27 V; RL = 60 Ω; Tvj = −40 °C to +150 °C; unless speciﬁed
otherwise; all voltages are deﬁned with respect to ground; positive currents ﬂow into the device.[1]
Supplies (pins VBAT, VCC and VI/O)
VCC(sleep) VCC undervoltage detection
level for forced Sleep mode
VBAT = 12 V (fail-safe) 2.75 3.3 4.5 V
VI/O(sleep) VI/O undervoltage detection
level for forced Sleep mode
0.5 1.5 2 V
VBAT(stb) VBAT voltage level for fail-safe
fallback mode
VCC = 5 V (fail-safe) 2.75 3.3 4.5 V
VBAT(pwon) VBAT voltage level for setting
pwon ﬂag
VCC = 0 V 2.5 3.3 4.1 V
ICC VCC input current normal mode; VTXD = 0 V
(dominant) 55 80 mA
normal or pwon/listen-only
mode; VTXD = VI/O (recessive) 6 10 mA
Standby or Sleep mode - 1 10 μA
II/O VI/O input current normal mode; VTXD = 0 V
(dominant)
100 350 1000 μA
normal or pwon/listen-only
mode; VTXD = VI/O (recessive) 80 200 μA
Standby or Sleep mode - 0 5 μA
IBAT VBAT input current normal or pwon/listen-only
mode 30 40 μA
Standby mode; VCC > 4.75 V;
VI/O = 2.8 V;
VINH =VWAKE =VBAT = 12 V 20 30 μA
Sleep mode;
VINH =VCC =VI/O = 0 V;
VWAKE =VBAT = 12 V 20 30 μA
Transmitter data input (pin TXD)
VIH HIGH-level input voltage 0.7VI/O -VCC + 0.3 V
VIL LOW-level input voltage −0.3 - +0.3VI/O V
IIH HIGH-level input current normal or pwon/listen-only
mode; VTXD = VI/O
−50 +5 μA
NXP Semiconductors TJA1041
High speed CAN transceiver
IIL LOW-level input current normal or pwon/listen-only
mode; VTXD = 0.3VI/O
−70 −250 −500 μA input capacitance not tested - 5 10 pF
Receiver data output (pin RXD)
IOH HIGH-level output current VRXD = VI/O − 0.4 V; VI/O = VCC −1 −3 −6mA
IOL LOW-level output current VRXD = 0.4 V; VTXD = VI/O; bus
dominant 5 12 mA
Standby and enable control inputs (pins STB and EN)
VIH HIGH-level input voltage 0.7VI/O -VCC + 0.3 V
VIL LOW-level input voltage −0.3 - +0.3VI/O V
IIH HIGH-level input current VSTB = VEN = 0.7VI/O 14 10 μA
IIL LOW-level input current VSTB = VEN = 0 V - 0 −1 μA
Error and power-on indication output (pin ERR)
IOH HIGH-level output current VERR = VI/O − 0.4 V; VI/O = VCC −4 −20 −50 μA
IOL LOW-level output current VERR = 0.4 V 0.1 0.2 0.35 mA
Local wake-up input (pin WAKE)
IIH HIGH-level input current VWAKE = VBAT − 1.9 V −1 −5 −10 μA
IIL LOW-level input current VWAKE = VBAT − 3.1 V 1 5 10 μA
Vth threshold voltage VSTB = 0 V VBAT − 3VBAT − 2.5 VBAT − 2V
Inhibit output (pin INH)
ΔVH HIGH-level voltage drop IINH = −0.18 mA 0.05 0.2 0.8 V
|IL| leakage current Sleep mode - 0 5 μA
Bus lines (pins CANH and CANL)
VO(dom) dominant output voltage VTXD = 0 V
pin CANH 3 3.6 4.25 V
pin CANL 0.5 1.4 1.75 V
VO(dom)(m) matching of dominant output
voltage (VCC - VCANH - VCANL)
−0.1 - +0.15 V
VO(dif)(bus) differential bus output voltage
(VCANH - VCANL)
VTXD = 0 V (dominant);Ω 1.5 - 3.0 V
VTXD = VI/O (recessive); no load −50 - +50 mV
VO(reces) recessive output voltage normal or pwon/listen-only
mode; VTXD = VI/O; no load 0.5VCC 3V
Standby or Sleep mode; no load −0.1 0 +0.1 V
IO(sc) short-circuit output current VTXD = 0 V (dominant)
pin CANH; VCANH = 0 V −45 −70 −95 mA
pin CANL; VCANL = 40 V 45 70 95 mA
IO(reces) recessive output current −27 V < VCAN < 32 V −2.5 - +2.5 mA
Table 8. Characteristics …continued
VCC = 4.75 V to 5.25 V; VI/O = 2.8 V to VCC; VBAT = 5 V to 27 V; RL = 60 Ω; Tvj = −40 °C to +150 °C; unless speciﬁed
otherwise; all voltages are deﬁned with respect to ground; positive currents ﬂow into the device.[1]

Partno	Mfg	Dc	Qty	Available	Descript
TJA1041T	PHILIPS	N/a	316	avai	High-speed CAN transceiver with standby and sleep mode