TEA5170 ,SWITCH MODE POWER SUPPLY SECONDARY CIRCUITTEA5170SWITCH MODE POWER SUPPLY SECONDARY CIRCUIT.INTERNAL PWM SIGNAL GENERATOR.POWER SUPPLY WIDE R ..
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TEA5170
SWITCH MODE POWER SUPPLY SECONDARY CIRCUIT
TEA5170SWITCH MODE POWER SUPPLY SECONDARY CIRCUIT
September 1993
PIN CONNECTIONS INTERNAL PWM SIGNAL GENERATOR. POWER SUPPLY WIDE RANGE 4.5V – 14.5V. SOFT START. REFERENCE VOLTAGE 2V ± 5%. WIDE FREQUENCY RANGE 250kHz. MINIMUM OUTPUT PULSE WIDTH 500nS. MAXIMUM PRESET DUTY CYCLE. SYNCHRONIZATION WINDOW. OUTPUT SWITCH. UNDERVOLTAGE LOCKOUT. FREQUENCY RANGE WITH SYNCHRONIZA-
TION 64kHz
DESCRIPTIONThe TEA5170 is designed to work in the secondary
part of an off-line SMPS, sending pulses to the
slaved TEA2260/61 which are located on the pri-
mary side of the main transformer. An accurate
regulated voltage is obtained by duty cycle control.
The TEA5170 can be externally synchronized by
higher or lower frequency signal, then it could be
used in applications like TV set ones. For more
details, refer to application note AN408/0591.
1/9
BLOCK DIAGRAM
ABSOLUTE MAXIMUM RATINGS
THERMAL DATA
RECOMMANDED OPERATING CONDITIONS
TEA51702/9
ELECTRICAL CHARACTERISTICS (TA = 25o C, VCC = 12V, unless otherwise specified)
OSCILLATOR
ERROR VOLTAGE AMPLIFIER (VCC = 12V)
INTERNAL VOLTAGE REFERENCE
TON MIN
POWER OUTPUT STAGE
SYNCHRONISATION
SOFT START
*Csf is a high impedance capacitor
TEA51703/9
ELECTRICAL CHARACTERISTICS (TA = 25o C, VCC = 12V, unless otherwise specified) (continued)
VCC MONITOR
TOTAL DEVICE
GENERAL DESCRIPTIONThe TEA5170 takes place in the secondary part of
an isolated off-line SMPS. During normal mode
operation, it sends pulses to the slave circuit lo-
cated in the primary side (TEA2164, TEA2260/61)
through a pulse transformer to achieve a very
precisely regulated voltage by duty cycle control.
The main blocs of the circuit are : an error voltage amplifier an RC oscillator an output stage
-a VCC monitor a voltage reference bloc a pulse width modulator two logic blocs a soft start and Duty cycle limiting bloc
PRINCIPLE OF OPERATIONThe TEA5170 sends pulses continuously to the
slave circuit in order to insure a proper behaviour
of the primary side. According to this, the output duty cycle is varying
between DON (min.) (0.05) and DON (max.) (0.75) :
then even in case of open load, pulses are still
sent to the slave circuit.
Figure 1 : Basic Concept
ASYNCHRONIZED MODE (Figure 2)The regulated voltage image is compared to 2V
vol-tage reference. The error voltage amplifier out-
put and the RC oscillator voltage ramp are applied
to the internal Pulse Width Modulator Inputs.
The PWM logic Output is connected to a logic bloc
which behaves like a RS latch, sets by the PWM
output and resets when Ct downloading occurs.
Finally, the push-pull output bloc delivers square
wave signal whom output leading edge occurs
during Ct uploading time, and output trailing edge
at Ct downloading time end. The duty cycle is
limited to 75% of oscillator period as maximum
value and to Ct downloading time/oscillator period
as minimum value (Figure 2).
Figure 2
SYNCHRONIZED MODE (see Figure 3)The TEA5170 will enter the Synchronized Mode
when it receives one pulse through Rt during Ct
discharge.
At that time Ct charging current will be multiplied
by 0.75 and period will increase up to To x 1.26.
A pulse occuring during the synchro window, com-
mands the Ct downloading. If none, the TEA5170
will return to normal mode at the end of the period.
TEA51704/9
Figure 3
Remark : In case of an application between
TEA5170 and TEA2164, to optimize the
synchronization windows of these
circuits, the following relations have to
be used : Tm = TSYNC
1.06 Te = Tm
with Te : Free period of the TEA2164
oscillator, and Tm : Free period of the
TEA5170 oscillator.
BLOCK DESCRIPTIONThe error voltage amplifier inverting-input and out-
put are accessible to use different feed-back net-
work and allowing parasitic filtering network. The
non-inverting input is internaly connected to 2V
reference voltage.
The RC oscillator is designed to work at high
frequency (up to 250kHz). RT sets the capacitor
charging current Io = 2/RT.
The capacitor CT is loaded from V1 ≈ 1V to V2 = 2V
during T1 = CT RT
1.985 and then down loaded through
an integrated resistor R2 ≈ 1kΩ during T2 = 1300 CT
The ramp is used to limit the duty cycle. Then the
maximum duty cycle is
DONMAX = 1
T1 + T2 (0.73 T1 + T2)
The output level is VCC independant when VCC is
over 8V.
The VCC monitoring switches the circuit on when
VCC is over 4V and switches it off when under 3.8V.
This function insures a proper starting procedure
(made by the primary side circuit).
SYNCHRONIZATION(see Figures 4 and 5)
Figure 4 : Triggering Schematic
Figure 5 : Typical Waveforms
TEA51705/9
STARTINGWhen VCC is under 4V, output pulses are not
allowed and the slave circuit keeps its own mode.
When VCC is going over 4V, output pulses are sent
via the pulse transformer (or an optical device) to
the slave circuit which is synchronizing and enter-
ing the slaved mode. Output pulses can be shut
down only if VCC goes below 3.8 Volt.
SOFT STARTUsing Csf, it is possible to make a soft start se-
quence. When VCC grows from 0V to 4V, voltage
on Csf equals 0V. When VCC is higher than 4V, Csf
is loaded by a 3.7μA current, then TonMAX (Vcsf)
will vary linearly from Tonmin to Tonmax according
to Csfst bias.
When VCC will go low (3.8 Volt threshold), Csf will
be downloaded by an internal transistor.
Figure 6 : Soft-Start Sequence
Figure 7 : Electrical Schematic
POWER OUTPUT STAGE
TEA51706/9
