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TEA1753LT
HV start-up DCM/QR flyback controller with integrated DCM/QR PFC controller
1. General descriptionThe TEA1753LT is the third generation of green Switched Mode Power Supply (SMPS)
controller ICs. The TEA1753LT combines a controller for Power Factor Correction (PFC)
and a flyback controller. Its high level of integration allows the design of a cost-effective
power supply with a very low number of external components.
The special built-in green functions provide high efficiency at all power levels. This
efficiency applies to quasi-resonant operation at high-power levels, quasi-resonant
operation with valley skipping, as well as to reduced frequency operation at lower power
levels. At low-power levels, the PFC switches off to maintain high efficiency.
During low-power conditions, the flyback controller switches to frequency reduction mode
and limits the peak current to an adjustable minimum value. This mode ensures high
efficiency at low-power and good standby power performance while minimizing audible
noise from the transformer.
The controller can be switched to the power-down mode for no-load operation. In this
mode, the controller is shut down for very low standby power applications
The TEA1753LT is a Multi-Chip Module (MCM), containing 2 chips. The proprietary
high-voltage BCD800 process which makes direct start-up possible from the rectified
universal mains voltage in an effective and green way. The second low voltage
Silicon On Insulator (SOI) is used for accurate, high-speed protection functions and
control.
The TEA1753LT enables the design of highly efficient and reliable supplies with power
requirements of up to 250 W using a minimum number of external components.
Remark: All values provided throughout the running text, are typical values unless otherwise stated.
TEA1753LT
HV start-up DCM/QR flyback controller with integrated
DCM/QR PFC controller
Rev. 3 — 24 August 2012 Product data sheet
NXP Semiconductors TEA1753LT
HV start-up flyback controller with integrated PFC controller
2. Features and benefits
2.1 Distinctive features Integrated PFC and flyback controller Universal mains supply operation (70V (AC) to 276V (AC)) Dual-boost PFC with accurate maximum output voltage (NXP patented) High level of integration, resulting in a very low external component count and a
cost-effective design Adjustable PFC switch-off delay
2.2 Green features On-chip start-up current source Power down functionality for very low standby power
2.3 PFC green features Valley/zero voltage switching (ZVS) for minimum switching losses (NXP patented) Frequency limitation to reduce switching losses PFC is switched off when a low load is detected at the flyback output
2.4 Flyback green features Valley switching for minimum switching losses (NXP patented) Frequency reduction with adjustable minimum peak current at low-power operation to
maintain high efficiency at low output power levels
2.5 Protection features Safe restart mode for system fault conditions Continuous mode protection with demagnetization detection for both converters (NXP
patented) UnderVoltage Protection (UVP) (foldback during overload) Accurate OverVoltage Protection (OVP) for both converters (adjustable for flyback
converter) Mains voltage independent OverPower Protection (OPP) Open control loop protection for both converters. The open-loop protection on the
flyback converter is latched OverTemperature Protection (OTP) Low and adjustable OverCurrent Protection (OCP) trip level for both converters General-purpose latched protection input for system OverTemperature Protection
(OTP) for example
3. Applications The device is used in all applications requiring an efficient and cost-effective power
supply solution up to 250 W. Notebook adapters, in particular, benefit from the high
level of integration
NXP Semiconductors TEA1753LT
HV start-up flyback controller with integrated PFC controller
4. Ordering informationTable 1. Ordering informationTEA1753LT SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
NXP Semiconductors TEA1753LT
HV start-up flyback controller with integrated PFC controller
5. Block diagramNXP Semiconductors TEA1753LT
HV start-up flyback controller with integrated PFC controller
6. Pinning information
6.1 Pinning
6.2 Pin description
Table 2. Pin descriptionVCC 1 supply voltage
GND 2 ground
FBCTRL 3 flyback control input
FBAUX 4 auxiliary winding input for demagnetization timing and flyback OVP
LATCH 5 general-purpose protection input
PFCCOMP 6 frequency compensation pin for PFC
VINSENSE 7 mains voltage sense input
PFCAUX 8 auxiliary winding input for demagnetization timing for PFC
VOSENSE 9 sense input for PFC output voltage
FBSENSE 10 flyback current sense input
PFCSENSE 11 PFC current sense input
PFCDRIVER 12 PFC gate-driver output
FBDRIVER 13 flyback gate-driver output
PFCTIMER 14 delay timer pin for PFC on/off control
HVS 15 high-voltage safety spacer, not connected 16 high-voltage start-up/ flyback valley sensing
NXP Semiconductors TEA1753LT
HV start-up flyback controller with integrated PFC controller
7. Functional description
7.1 General controlThe TEA1753LT contains a controller for a power factor correction circuit as well as a
controller for a flyback circuit. A typical configuration is shown in Figure3.
7.1.1 Start-up and UnderVoltage LockOut (UVLO)Initially the capacitor on the VCC pin is charged from the high-voltage mains using the HV
pin.
When VCC is less than Vtrip, the charge current is low. This low current protects the IC if
the VCC pin is shorted to ground. To ensure a short start-up time, the charge current above
Vtrip is increased until VCC reaches Vth(UVLO). When VCC is between Vth(UVLO) and Vstartup,
the charge current returns to low to ensure a low safe restart duty cycle during fault
conditions.
The control logic activates the internal circuitry and switches off the HV charge current
when the voltage on pin VCC passes the Vstartup level. First, the LATCH pin current source
is activated and the soft-start capacitors on the PFCSENSE and FBSENSE pins are
charged. Also the clamp circuit on the PFCCOMP pin is activated.
The PFC circuit is activated when the following conditions are met:
the LATCH pin voltage exceeds the Ven(LATCH) voltage
the PFCCOMP pin voltage reaches the Ven(PFCCOMP) voltage
the soft-start capacitor on the PFCSENSE pin is charged
NXP Semiconductors TEA1753LT
HV start-up flyback controller with integrated PFC controllerIf the soft start capacitor on the FBSENSE pin is charged, the flyback converter is also
activated. The flyback converter output voltage is then regulated to its nominal output
voltage. The auxiliary winding of the flyback converter takes over the IC supply. See
Figure4.
If during start-up the LATCH pin does not reach the Ven(LATCH) level before VCC reaches
Vth(UVLO), it is deactivated. The charge current is then switched on again.
When the flyback converter starts, VFBCTRL is monitored. If this output voltage does not
reach its intended regulation level within a specified time, the voltage on the FBCTRL pin
reaches the Vto(FBCTRL) level. An error is then assumed and a latched protection is
initiated.
When one of the protection functions is activated, both converters stop switching and the
VCC voltage drops to Vth(UVLO). A latched protection recharges capacitor CVCC using the
HV pin, but does not restart the converters. To provide safe restart protection, the
capacitor is recharged using the HV pin and the device restarts (see block diagram,
Figure1).
If OVP of the PFC circuit (VVOSENSE >VOVP(VOSENSE)) occurs, the PFC controller stops
switching until the VOSENSE pin voltage drops to less than VOVP(VOSENSE). If a mains
undervoltage is detected, VVINSENSE
until VVINSENSE >Vstart(VINSENSE) again.
When the voltage on the VCC pin drops below the undervoltage lockout level, both
controllers stop switching and re-enter the safe restart mode. In the safe restart mode, the
driver outputs are disabled and the VCC pin voltage is recharged using the HV pin.
NXP Semiconductors TEA1753LT
HV start-up flyback controller with integrated PFC controller 7.1.5)
NXP Semiconductors TEA1753LT
HV start-up flyback controller with integrated PFC controller
7.1.3 Supply management
All internal reference voltages are derived from a temperature compensated and trimmed
on-chip band gap circuit. Internal reference currents are derived from a temperature
compensated and trimmed on-chip current reference circuit.
7.1.4 Latch input
The LATCH pin is a general-purpose input pin, which is used to switch off both converters.
The pin sources a current IO(LATCH) of80 A. Switching is stopped as soon as the voltage
on this pin drops below 1.25V.
At initial start-up, switching is inhibited until the capacitor on the LATCH pin is charged
above 1.35 V. No internal filtering is done on this pin. An internal Zener clamp of 2.9V
protects this pin from excessive voltages.
7.1.5 Fast latch reset
In a typical application, the mains is interrupted briefly to reset the latched protection. The
PFC bus capacitor, Cbus, does not have to discharge for this latched protection to reset.
When the VINSENSE voltage drops below 750 mV and is then raised to 870 mV, the
latched protection is reset.
The latched protection is also reset by removing the voltage on the VCC and HV pins.
7.1.6 Overtemperature protection
An accurate internal temperature protection is provided in the circuit. When the junction
temperature exceeds the thermal shut-down temperature, the IC stops switching. As long
as OTP is active, the capacitor CVCC is not recharged from the HV mains. If the VCC
supply voltage is not sufficient, the OTP circuit is supplied from the HV pin.
OTP is a latched protection. It is reset by removing the voltage on the VCC and HV pins or
by the fast latch reset function. (See Section 7.1.5)
7.2 Power factor correction circuit
The power factor correction circuit operates in quasi-resonant or Discontinuous
Conduction Mode (CDM) with valley switching. The next primary stroke is only started
when the previous secondary stroke has ended and the voltage across the PFC MOSFET
has reached a minimum value. VPFCAUX is used to detect transformer demagnetization
and the minimum voltage across the external PFC MOSFET switch.
7.2.1 ton control
The power factor correction circuit is operated in ton control. The resulting mains harmonic
reduction is well within the class-D requirements.
7.2.2 Valley switching and demagnetization (PFCAUX pin)
The PFC MOSFET is switched on after the transformer is demagnetized. Internal circuitry
connected to the PFCAUX pin detects the end of the secondary stroke. It also detects the
voltage across the PFC MOSFET. To reduce switching losses and electromagnetic
Interference (EMI) (valley switching), the next stroke is started if the voltage across the
PFC MOSFET is at its minimum.
NXP Semiconductors TEA1753LT
HV start-up flyback controller with integrated PFC controller
If a demagnetization signal is not detected on the PFCAUX pin, the controller generates a
Zero Current Signal (ZCS), 50 s after the last PFCGATE signal.
If a valley signal is not detected on the PFCAUX pin, the controller generates a valley
signal 4 s after demagnetization is detected.
To protect the internal circuitry during lightning events, for example, add a 5 k series
resistor to PFCAUX. To prevent incorrect switching due to external disturbance, place the
resistor close to the IC on the printed-circuit board.
7.2.3 Frequency limitation
To optimize the transformer and minimize switching losses, the switching frequency is
limited to fsw(PFC)max. If the frequency for quasi-resonant operation is above the fsw(PFC)max
limit, the system switches over to DCM. The PFC MOSFET is only switched on at a
minimum voltage across the switch (valley switching).
7.2.4 Mains voltage compensation (VINSENSE pin)
The equation for the transfer function of a power factor corrector contains the square of
the mains input voltage. In a typical application this results in a low bandwidth for low mains input voltages and a high bandwidth for high mains input voltages.
To compensate for the mains input voltage influence, TEA1753LT contains a correction
circuit. The average input voltage is measured using the VINSENSE pin and the
information is fed to an internal compensation circuit. Using this compensation, it is
possible to keep the regulation loop bandwidth constant over the mains input range. This
yields a fast transient response on load steps, while still complying with class-D MHR
requirements.
In a typical application, a resistor and two capacitors on the PFCCOMP pin set the
bandwidth of the regulation loop.
7.2.5 Soft start-up (PFCSENSE pin)
To prevent audible transformer noise at start-up or during hiccup, the soft-start function
slowly increases the transformer peak current. This increase is achieved by inserting RSS1
and CSS1 between the PFCSENSE pin and current sense resistor RSENSE1. An internal
current source charges the capacitor to:
(1)
The voltage is limited to Vstart(soft)PFC.
The start level and the time constant of the increasing primary current level is adjusted
externally by changing the values of RSS1 and CSS1.
(2)
The charging current Istart(soft)PFC flows as long as VPFCSENSE is below 0.5 V. If VPFCSENSE
exceeds 0.5 V, the soft-start current source starts limiting current Istart(soft)PFC. When the
PFC starts switching, the Istart(soft)PFC current source is switched off; see Figure5.
NXP Semiconductors TEA1753LT
HV start-up flyback controller with integrated PFC controller
7.2.6 Low-power mode
When the output power of the flyback converter (see Section 7.3) is low, the flyback
converter switches over to frequency modulation mode. When the maximum switching
frequency of the flyback drops below 48 kHz, the power factor correction circuit is
switched off to maintain high efficiency. Connect a capacitor to the PFCTIMER pin to delay
switching off (see also Section 7.2.7).
During low-power mode operation, the PFCCOMP pin is clamped to a minimum voltage of
3.5V or 2.5 V and a maximum voltage of 3.9 V. The lower clamp voltage depends on the
voltage on VINSENSE pin. This voltage limits the maximum power that is delivered when
the PFC is switched on again. The upper clamp voltage ensures that the PFC returns from
low-power mode to its normal regulation point in a limited time.
When the maximum switching frequency of the flyback converter exceeds 86 kHz, the
power factor correction circuit restores normal operation.
7.2.7 PFC off delay (pin PFCTIMER)
When the flyback converter maximum frequency drops below 48 kHz, the PFC is
switched off. The IC then outputs a 5 A current to the PFCTIMER pin. When the voltage
on the PFCTIMER pin reaches 3.6 V, the PFC is switched off by performing a soft-stop.
When the flyback converter frequency exceeds 86 kHz, a switch discharges the
PFCTIMER pin capacitor. When the voltage on the PCTIMER pin drops below 1.27 V, the
PFC is switched on (see Figure 6).
NXP Semiconductors TEA1753LT
HV start-up flyback controller with integrated PFC controller
7.2.8 Dual-boost PFC
The mains input voltage modulates the PFC output voltage. The mains input voltage is
measured using the VINSENSE pin. If the voltage on the VINSENSE pin drops below
2.2 V, the current is sourced from the VOSENSE pin. To ensure the stable switch-over, a
200 mV transition region is inserted around the 2.2 V, see Figure7.
For low VINSENSE input voltages, the output current is 8 A. This output current, in
combination with the resistors on the VOSENSE pin, sets the lower PFC output voltage
level at low mains voltages. At high mains input voltages, the current is switched to zero.
The PFC output voltage is then at its maximum. As this current is zero in this situation, it
does not affect the accuracy of the PFC output voltage.
For proper switch-off, the VOSENSE current is switched to its maximum value of 8 A
when the voltage on pin VOSENSE drops below 2.1V.
7.2.9 Overcurrent protection (PFCSENSE pin)
The maximum peak current is limited cycle-by-cycle by sensing the voltage across an
external sense resistor, RSENSE1, on the source of the external MOSFET . The voltage is
measured using the PFCSENSE pin.
7.2.10 Mains undervoltage lockout/brownout protection (VINSENSE pin)
To prevent the PFC from operating at very low mains input voltages, the voltage on the
VINSENSE pin is continuously sensed. When the voltage on this pin drops below the
Vstop(VINSENSE) level, switching of the PFC is stopped.
7.2.11 Overvoltage protection (VOSENSE pin)
To prevent output overvoltage during load steps and mains transients, an overvoltage
protection circuit is built in.
When the voltage on the VOSENSE pin exceeds the Vovp(VOSENSE) level, switching of the
power factor correction circuit is inhibited. Switching of the PFC recommences when the
VOSENSE pin voltage drops below the Vovp(VOSENSE) level again.
When the resistor between the VOSENSE pin and ground is open, the overvoltage
protection is also triggered.
NXP Semiconductors TEA1753LT
HV start-up flyback controller with integrated PFC controller
7.2.12 PFC open-loop protection (VOSENSE pin)
The power factor correction circuit does not start switching until the voltage on the
VOSENSE pin is above the Vth(ol)(VOSENSE) level. This feature protects the circuit from
open-loop and VOSENSE short-circuit.
7.2.13 Driver (PFCDRIVER pin)
The driver circuit to the gate of the power MOSFET has a current sourcing capability of
500 mA and a current sink capability of 1.2 A. These capabilities permit fast turn-on and
turn-off of the power MOSFET for efficient operation.
7.3 Flyback controller
The TEA1753LT includes a controller for a flyback converter. The flyback converter
operates in quasi-resonant or DCM with valley switching. The auxiliary winding of the
flyback transformer provides demagnetization detection and powers the IC after start-up.
7.3.1 Multimode operation
The TEA1753LT flyback controller operates in several modes; see Figure8.
At high output power the converter switches to quasi-resonant mode. The next converter
stroke starts after demagnetization of the transformer and detection of the valley. In
quasi-resonant mode switching losses are minimized. This minimization is achieved by
the converter only switching on when the voltage across the external MOSFET is at its
minimum (see also Section 7.3.2).
To prevent high frequency operation at low loads, the maximum switching frequency is
limited to 125 kHz. When the frequency limit is reached, the quasi-resonant operation
changes to DCM with valley skipping. This mode limits the MOSFET switch-on losses and
conducted EMI.
NXP Semiconductors TEA1753LT
HV start-up flyback controller with integrated PFC controller
A Voltage Controlled Oscillator (VCO) controls the frequency at very low power and
standby levels. The minimum frequency is reduced to zero. During frequency reduction
mode, the primary peak current is kept at an adjustable minimal level to maintain a high
efficiency. As the primary peak current is low in frequency reduction operation, no audible
noise is noticeable at switching frequencies in the audible range. Valley switching is also
active in this mode.
In frequency reduction mode, the PFC controller is switched off. The flyback maximum
frequency changes linearly with the control voltage on the FBCTRL pin (see Figure 9).
Hysteresis has been added for stable on and off switching of the PFC. At no-load
operation, the switching frequency is reduced to (almost) zero.
The input voltage of the flyback converter and the capacitance on the drain node of the
flyback power switch affect the frequency reduction slope. By choosing the proper
compensation, the frequency reduction slope for high input voltages is chosen as the
same as for low input voltages. This compensation yields an input voltage independent
PFC switch-on and switch-off power level (see the application information in Section 11).
7.3.2 Valley switching (HV pin)
A new cycle starts when the external MOSFET is switched on. VFBSENSE and VFBCTRL
determine the on-time. The MOSFET is then switched off and the secondary stroke starts.
After the secondary stroke, the drain voltage shows an oscillation with a frequency of
approximately:
(3)
where Lp is the primary self-inductance of the flyback transformer and Cd is the
capacitance on the drain node.
When the internal oscillator voltage is high and the secondary stroke ended, the circuit
NXP Semiconductors TEA1753LT
HV start-up flyback controller with integrated PFC controller
Figure 10 shows the drain voltage, valley signal, secondary stroke signal and the internal
oscillator signal.
Valley switching allows high frequency operation as capacitive switching losses are
reduced, see Equation 4. High frequency operation makes small and cost-effective
magnetic components possible.
(4)
7.3.3 Current mode control (FBSENSE pin)
Current mode control is used for the flyback converter for its good line regulation.
The FBSENSE pin senses the primary current across an external resistor and compares it
with an internal control voltage. The internal control voltage is proportional to the FBCTRL
pin voltage, see Figure 11.
The FBSENSE pin outputs a current of 3 A. This current runs through the resistors from
the FBSENSE pin to the sense resistor and creates an offset voltage. The minimum peak
current of the flyback is adjusted using this offset voltage. Adjusting the minimum peak
current level, changes the frequency reduction slope (see Figure8).
NXP Semiconductors TEA1753LT
HV start-up flyback controller with integrated PFC controller
The driver output is latched in the logic, preventing multiple switch-on.
7.3.4 Demagnetization (FBAUX pin)
The system is always in QR or DCM. The internal oscillator does not start a new primary
stroke until the previous secondary stroke has ended.
Demagnetization features a cycle-by-cycle output short-circuit protection by immediately
lowering the frequency (longer off-time), thus reducing the power level.
Demagnetization recognition is suppressed during the first tsup(xfmr_ring) time of 2 s. This
suppression is necessary at low output voltages and at start-up. It is also required in
applications where the transformer has a large leakage inductance.
If the FBAUX pin is open-circuit or not connected, a fault condition is assumed and the
converter immediately stops. Operation restarts as soon as the fault condition is removed.
7.3.5 Flyback control/time-out (FBCTRL pin)
The FBCTRL pin is connected to an internal voltage source of 3.5 V using an internal
resistor of 3 k. When the voltage on this pin exceeds 2.5 V, the connection is disabled
and the pin is biased with a small current. If the voltage on this pin exceeds 4.5 V, a fault is
assumed, switching is stopped and a latched protection is activated.
If a capacitor and a resistor are connected in series to this pin, a time-out function is
created to protect against an open control loop. See Figure 12 and Figure 13. The
time-out function is disabled by connecting a resistor (100 k) to ground on the FBCTRL
pin.
If the pin is short-circuited to ground, switching of the flyback controller is prevented.
During normal operating conditions, the converter regulates the output voltage. The
voltage on the FBCTRL pin is then between 1.3 V for the minimum output power and 2 V
for the maximum output power.
