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TEA1750T
HV start-up DCM/QR flyback controller with integrated DCM/QR PFC controller
General descriptionThe GreenChip III is the third generation of green Switched Mode Power Supply (SMPS)
controller ICs. The TEA1750 combinesa controllerfor Power Factor Correction (PFC) and flyback controller.Its high levelof integration allows the designofa cost-effective power
supply with a very low number of external components.
The special built-in green functions provide high efficiencyatall power levels. This applies
to quasi-resonant operation at high power levels, quasi-resonant operation with valley
skipping, as well as to reduced frequency operation at lower power levels. At low power
levels, the PFC switches over to burst mode control to maintain high efficiency. In burst
mode, soft-start and soft-stop functions are added to eliminate audible noise.
During low power conditions, the flyback controller switches to frequency reduction mode
and limits the peak current to 25 % of its maximum value. This will ensure high efficiency
at low power and good standby power performance while minimizing audible noise from
the transformer.
The proprietary high voltage BCD800 process makes direct start-up possible from the
rectified universal mains voltage in an effective and green way. A second low voltage
Silicon On Insulator (SOI) IC is used for accurate, high speed protection functions and
control.
The TEA1750 enables highly efficient and reliable supplies with power requirementsupto
250 W, to be designed easily and with the minimum number of external components.
Features
2.1 Distinctive features Integrated PFC and flyback controller Universal mains supply operation (70 V AC to 276V AC) High level of integration, resulting in a very low external component count and a
cost-effective design
2.2 Green features On-chip start-up current source
2.3 PFC green features Valley/zero voltage switching for minimum switching losses (patented) Frequency limitation to reduce switching losses Burst mode operation if a low load is detected at the flyback output (patented)
TEA1750
GreenChip III SMPS control IC
Rev. 02 — 15 December 2008 Product data sheet
NXP Semiconductors TEA1750
GreenChip III SMPS control IC
2.4 Flyback green features Valley switching for minimum switching losses (patented) Frequency reduction with fixed minimum peak current at low power operation to
maintain high efficiency at low output power levels
2.5 Protection features Safe restart mode for system fault conditions Continuous mode protection by means of demagnetization detection for both
converters (patented) UnderVoltage Protection (UVP) (foldback during overload) Accurate OverVoltage Protection (OVP) for both converters (adjustable for flyback
converter) Open control loop protection for both converters IC OverTemperature Protection (OTP) Low and adjustable OverCurrent Protection (OCP) trip level for both converters Soft (re)start for both converters Soft stop PFC to minimize audible noise Mains UnderVoltage Protection (UVP)/ brownout protection General purpose input for latched protection, e.g. to be used for system
Overtemperature protection
Applications The device can be used in all applications that require an efficient and cost-effective
power supply solution up to 250 W. Notebook adapters in particular can benefit from
the high level of integration.
Ordering information
Table 1. Ordering informationTEA1750T SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
NXP Semiconductors TEA1750
GreenChip III SMPS control IC Block diagram
NXP Semiconductors TEA1750
GreenChip III SMPS control IC Pinning information
6.1 Pinning
6.2 Pin description
Table 2. Pin descriptionVCC 1 supply voltage
GND 2 ground
FBCTRL 3 control input for flyback
FBAUX 4 input from auxiliary winding for demagnetization timing and
overvoltage protection for flyback
LATCH 5 general purpose protection input
PFCCOMP 6 frequency compensation pin for PFC
VINSENSE 7 sense input for mains voltage
PFCAUX 8 input from auxiliary winding for demagnetization timing for PFC
VOSENSE 9 sense input for PFC output voltage
FBSENSE 10 programmable current sense input for flyback
PFCSENSE 11 programmable current sense input for PFC
PFCDRIVER 12 gate driver output for PFC
FBDRIVER 13 gate driver output for flyback
HVS 14, 15 high voltage safety spacer, not connected 16 high voltage start-up and valley sensing of flyback part
NXP Semiconductors TEA1750
GreenChip III SMPS control IC Functional description
7.1 General controlThe TEA1750 contains a controller for a power factor correction circuit as well as a
controller for a flyback circuit. A typical configuration is shown in Figure3.
7.1.1 Start-up and undervoltage lock-outInitially the capacitoron the VCC pinis charged from the high voltage mains via the HV pin.
As long as VCC is below Vtrip, the charge current is low. This protects the IC in case the
VCC pin is shorted to ground. For a short start-up time the charge current above Vtrip is
increased until VCC reaches Vth(UVLO). If VCC is between Vth(UVLO) and Vstartup, the charge
current is low again, ensuring a low duty cycle during fault conditions.
The control logic activates the internal circuitry and switches off the charge current when
the voltage on pin VCC passes the Vstartup level. First, the LA TCH pin output is activated
and the soft-start capacitors on the PFCSENSE and FBSENSE pins are charged. When
the LA TCH pin voltage exceeds the Ven(LATCH) voltage and the soft-start capacitor on the
PFCSENSE pin is charged, the PFC circuit is activated. The supply current from the pin is then switched on again and the PFC circuit charges the Cbus capacitor. When
the voltageon pin VOSENSE reaches the Vstart(fb) level, the charge currentis switchedoff
and the flyback converteris activated (providing the soft-start capacitoron the FBSENSE
pinis charged). The output voltageof the flyback converteris then regulatedtoits nominal
output voltage. The IC supply is taken over by the auxiliary winding of the flyback
converter. See Figure4.
NXP Semiconductors TEA1750
GreenChip III SMPS control ICWhen the PFC is started, there is initially no supply take-over from the auxiliary winding.
To make a small VCC capacitor possible, the VCC voltage is regulated to the Vstartup level,
as long as the flyback converter has not yet started. Regulation is done by hysteretic
control with a limited (high level) charge current. The hysteresis is typically 300 mV.
If during start-up the LA TCH pin does not reach the Ven(LATCH) level before VCC reaches
Vth(UVLO), the LATCH pin output is de-activated and the charge current is switched on
again. soonas the flyback converteris started, the voltageon the FBCTRL pinis monitored.If
the output voltageof the flyback converter does not reachits intended regulation levelina
predefined time, the voltageon the FBCTRL pin reaches the Vto(FBCTRL) level andan error
is assumed. The TEA1750 then initiates a safe restart.
When one of the protection functions is activated, both converters stop switching and the
VCC voltage drops to Vth(UVLO). A latched protection recharges the VCC capacitor via the
HV pin, but does not restart the converters. For a safe-restart protection, the capacitor is
recharged via the HV pin and the device restarts (see Figure1)
In the event of an overvoltage protection of the PFC circuit
(VIon pin VOSENSE> Vovp(VOSENSE)), only the PFC controller stops switching until the
VOSENSE pin voltage drops below Vovp(VOSENSE) again. Also, if a mains undervoltage is
detected (VIon pin VINSENSE< Vstop(VINSENSE)), only the PFC controller stops switching
until VI on pin VINSENSE> Vstart(VINSENSE) again.
When the voltageon pin VCC drops below the undervoltage lock-out level, both controllers
stop switching and re-enter the safe restart mode. In the safe restart mode the driver
outputs are disabled and the VCC pin voltage is recharged via the HV pin.
NXP Semiconductors TEA1750
GreenChip III SMPS control IC
7.1.2 Supply managementAll internal reference voltages are derived froma temperature compensated and trimmed
on-chip band gap circuit. Internal reference currents are derived from a temperature
compensated and trimmed on-chip current reference circuit.
7.1.3 Latch inputPin LATCH is a general purpose input pin, which can be used to switch off both
converters. The pin sources a current, IO(LATCH) on pin LATCH (typ 80 μA). Switching of
both converters is stopped as soon as the voltage on this pin drops below 1.25V. initial start-up, switchingis inhibited until the voltageon the LATCH pinis above 1.35V
(typ). No internal filtering is done on this pin. An internal Zener clamp of 2.7V (typ)
protects this pin from excessive voltages.
NXP Semiconductors TEA1750
GreenChip III SMPS control IC
7.1.4 Fast latch reseta typical application, the mains canbe interrupted brieflyto reset the latched protection.
The PFC bus capacitor, Cbus, does not have to discharge for this latched protection to
reset.
Typically the PFC bus capacitor, Cbus, has to discharge for the VCC to drop to this reset
level. When the latched protection is set, the clamping circuit of the VINSENSE circuit is
disabled (see also Section 7.2.8). As soon as the VINSENSE voltage drops below
750 mV (typ) and then is raised to 870 mV (typ), the latched protection is reset.
The latched protection will also be reset by removing both the voltage on pin VCC and on
pin HV.
7.1.5 Overtemperature protection (OTP)An accurate internal temperature protection is provided in the circuit. When the junction
temperature exceeds the thermal shutdown temperature, the IC only stops switching. As
long as OTP is active, the VCC capacitor is not recharged from the HV mains. The OTP
circuit is supplied from the HV pin if the VCC supply voltage is not sufficient.
OTP is a latched protection. It can be reset by removing both the voltage on pin VCC and
on pin HV or by the fast latch reset function, see Section 7.1.4
7.2 Power factor correction circuitThe power factor correction circuit operatesin quasi-resonantor discontinuous conduction
mode with valley switching. The next primary stroke is only started when the previous
secondary stroke has ended and the voltage across the PFC MOSFET has reached a
minimum value. The voltage on the PFCAUX pin is used to detect transformer
demagnetization and the minimum voltage across the external PFC MOSFET switch.
7.2.1 ton controlThe power factor correction circuitis operatedinton control. The resulting mains harmonic
reduction of a typical application is well within the class-D requirements.
7.2.2 Valley switching and demagnetization (PFCAUX pin)The PFC MOSFETis switchedon after the transformeris demagnetized. Internal circuitry
connectedto the PFCAUX pin detects the endof the secondary stroke.It also detects the
voltage across the PFC MOSFET. The next strokeis startedif the voltage across the PFC
MOSFET is at its minimum in order to reduce switching losses and electromagnetic
interference (EMI) (valley switching).
If no demagnetization signal is detected on the PFCAUX pin, the controller generates a
zero current signal (ZCS), 50 μs (typ) after the last PFC gate signal.no valley signalis detectedon the PFCAUX pin, the controller generatesa valley signal μs (typ) after demagnetization was detected.
To protect the internal circuitry, for example during lightning events, it is advisable to add
a5kΩ series resistor to this pin. To prevent incorrect switching due to external
disturbance, the resistor should be placed close to the IC on the printed circuit board.
NXP Semiconductors TEA1750
GreenChip III SMPS control ICFor applications with high transformer ringing frequencies (after the secondary stroke),
the PFCAUX pin should be connected via a capacitor and a resistor to the auxiliary
winding. A diode must than be placed from the ground connection to the PFCAUX pin.
7.2.3 Frequency limitationTo optimize the transformer and minimize switching losses, the switching frequency is
limitedto fsw(PFC)max.If the frequencyfor quasi-resonant operationis above the fsw(PFC)max
limit, the system switches over to discontinuous conduction mode. Also here, the PFC
MOSFET is only switched on at a minimum voltage across the switch (valley switching).
7.2.4 Mains voltage compensation (VINSENSE pin)The mathematical equation for the transfer function of a power factor corrector contains
the square of the mains input voltage. In a typical application this results in a low
bandwidth for low mains input voltages, while at high mains input voltages the Mains
Harmonic Reduction (MHR) requirements may be hard to meet.
To compensate for the mains input voltage influence, the TEA1750 contains a correction
circuit. Via the VINSENSE pin the average input voltage is measured and the information fedtoan internal compensation circuit. With this compensationitis possibleto keep the
regulation loop bandwidth constant over the full mains input range, yieldinga fast transient
response on load steps, while still complying with class-D MHR requirements.
In a typical application, the bandwidth of the regulation loop is set by a resistor and two
capacitors on the PFCCOMP pin.
7.2.5 Soft start-up (pin PFCSENSE)To prevent audible transformer noise at start-up or during hiccup, the transformer peak
current, IDM, is increased slowly by the soft start function. This can be achieved by
inserting RSS1 and CSS1 between pin PFCSENSE and current sense resistor, RSENSE1. internal current source charges the capacitor to VPFCSENSE =Istart(soft)PFC× RSS1. The
voltage is limited to Vstart(soft)PFC.
The start level and the time constant of the increasing primary current level can be
adjusted externally by changing the values of RSS1 and CSS1.
The charging current Istart(soft)PFC flows as long as the voltage on pin PFCSENSE is
below 0.5 V (typ). If the voltage on pin PFCSENSE exceeds 0.5V , the soft start current
source starts limiting current Istart(soft)PFC. As soon as the PFC starts switching, the
Istart(soft)PFC current source is switched off; see Figure5. SoftStart 3RSS1× CSS1×=
NXP Semiconductors TEA1750
GreenChip III SMPS control IC
7.2.6 Burst mode controlWhen the output power of the flyback converter (see Section 7.3) is low, the flyback
converter switches overto frequency reduction mode. When frequency reduction modeis
enteredby the flyback controller, the power factor correction circuit switchesto burst mode
control.
In burst mode control, switching of the power factor correction circuit is inhibited until the
voltage on the VOSENSE pin has dropped to Vburst(L). Switching then restarts with a
soft-start to avoid audible noise (see Section 7.2.5). As soon as the voltage on the
VOSENSE pin reaches Vburst(H) the soft-stop circuit is activated, again to avoid audible
noise. During the soft-stop time the output voltage of the power factor correction circuit
overshoots, depending on the soft-start resistor and capacitor, RSS1 and CSS1, on the
PFCSENSE pin. As the Vburst(H) voltage is well below the Vreg(VOSENSE) voltage, the PFC
output voltage does not reach the normal operation output voltage of the power factor
correction circuit in a typical application due to this overshoot.
The burst mode repetition rate is defined by the output power and the value of the bus
capacitor, Cbus.
During burst mode operation the PFCCOMP pin is clamped between a voltage of
2.7V (typ) and 3.9 V (typ). The lower clamp voltage limits the maximum power that is
delivered during burst mode operation and yields a more sinusoidal input current during
the burst pulse. The upper clamp voltage ensures that the PFC can return to its normal
regulation point in a limited amount of time when returning from burst mode.
As soon as the flyback converter leaves frequency reduction mode, the power factor
correction circuit restores normal operation.To prevent continuouson andoff switchingof
the PFC circuit, a small hysteresis is built in (50 mV (typ) on the FBCTRL pin).
NXP Semiconductors TEA1750
GreenChip III SMPS control IC
7.2.7 Overcurrent protection (PFCSENSE pin)The maximum peak current is limited cycle-by-cycle by sensing the voltage across an
external sense resistor (RSENSE1) on the source of the external MOSFET. The voltage is
measured via the PFCSENSE pin.
7.2.8 Mains undervoltage lock-out / brownout protection (VINSENSE pin)To prevent the PFC from operating at very low mains input voltages, the voltage on the
VINSENSE pinis sensed continuously.As soonas the voltageon this pin drops below the
Vstop(VINSENSE) level, switchingof the PFCis stopped.If the low mains situation continues,
the PFC bus voltage eventually drops. The voltageon the VOSENSE pin then drops below
the Vstart(fb) level and the flyback converter is also disabled.
The voltage on pin VINSENSE is clamped to a minimum value,
(Vstart(VINSENSE) −ΔVpu(VINSENSE)) for a fast restart as soon as the mains input voltage is
restored after a mains dropout.
7.2.9 Overvoltage protection (VOSENSE pin)To prevent output overvoltage during load steps and mains transients, an overvoltage
protection circuit is built in. soonas the voltageon the VOSENSE pin exceeds the Vovp(VOSENSE) level, switchingof
the power factor correction circuit is inhibited. Switching of the PFC recommences as
soon as the VOSENSE pin voltage drops below the Vovp(VOSENSE) level again.
When the resistor between pin VOSENSE and groundis open, the overvoltage protection
is also triggered.
7.2.10 PFC open loop protection (VOSENSE pin)The power factor correction circuit does not start switching until the voltage on the
VOSENSE pin is above the Vth(ol)(VOSENSE) level. This protects the circuit from open loop
and VOSENSE short situations. As the VOSENSE pin draws a small input current,
switching is also inhibited when the pin is left open.
NXP Semiconductors TEA1750
GreenChip III SMPS control IC
7.2.11 Driver (pin PFCDRIVER)The driver circuit to the gate of the power MOSFET has a current sourcing capability of
typically 500 mA and a current sink capability of typically 1.2 A. This permits fast turn-on
and turn-off of the power MOSFET for efficient operation.
7.3 Flyback controllerThe TEA1750 includesa controllerfora flyback converter. The flyback converter operates
in quasi-resonant or discontinuous conduction mode with valley switching. The auxiliary
windingof the flyback transformer provides demagnetization detection and powers theIC
after start-up.
7.3.1 Multi mode operationThe TEA1750 flyback controller can operate in multi modes; see Figure7.
At high output power the converter switches to quasi-resonant mode. The next converter
strokeis started after demagnetizationof the transformer current.In quasi-resonant mode
switching losses are minimizedas the converter only switcheson when the voltage across
the external MOSFET is at its minimum (valley switching, see also Section 7.3.2). prevent high frequency operationat lower loads, the quasi-resonant operation changes
to discontinuous mode operation with valley skipping in which the switching frequency is
limited for EMI to fsw(fb)(max) (125 kHz typ). Again, the external MOSFET is only switched
on when the voltage across the MOSFET is at its minimum.
At very low power and standby levels the frequency is controlled down by a voltage
controlled oscillator (VCO). The minimum frequency can be reduced to zero. During
frequency reduction mode, the primary peak currentis keptata minimal levelof Ipkmax/4
to maintain a high efficiency. (Ipkmax is the maximum primary peak current set by the
sense resistor and the maximum sense voltage.) As the primary peak current is low in
frequency reduction mode operation (Ipk= Ipkmax/4), no audible noise is noticeable at
switching frequencies in the audible range. Valley switching is also active in this mode.
NXP Semiconductors TEA1750
GreenChip III SMPS control ICIn frequency reduction mode the PFC controller is switched to burst mode operation and
the flyback maximum frequency changes linearly with the control voltageon the FBCTRL
pin (see Figure8 ). For stable on-off switching of the PFC burst mode, the FBCTRL pin
has a 50 mV (typ) hysteresis. At no load operation the switching frequency of the flyback
can be reduced to (almost) zero.
7.3.2 Valley switching (HV pin)Refer to Figure 9. A new cycle starts when the external MOSFET is activated. After the
on-time (determinedby the FBSENSE voltage and the FBCTRL voltage), the MOSFETis
switchedoff and the secondary stroke starts. After the secondary stroke, the drain voltage
shows an oscillation with a frequency of approximately
where Lp is the primary self inductance of the flyback transformer and Cd is the
capacitance on the drain node.
As soon as the internal oscillator voltage is high again and the secondary stroke has
ended, the circuit waits for the lowest drain voltage before starting a new primary stroke.
Figure 9 shows the drain voltage, valley signal, secondary stroke signal and the internal
oscillator signal.
Valley switching allows high frequency operation as capacitive switching losses are
reduced, see Equation 1. High frequency operation makes small and cost-effective
magnetics possible.
(1) π×× ()---------------------------------------------------- 1--- Cd V2× f××=
NXP Semiconductors TEA1750
GreenChip III SMPS control IC
7.3.3 Current mode control (FBSENSE pin)Current mode control is used for the flyback converter for its good line regulation.
The primary current is sensed by the FBSENSE pin across an external resistor and
compared with an internal control voltage.The internal control voltage is proportional to
the FBCTRL pin voltage.
NXP Semiconductors TEA1750
GreenChip III SMPS control ICThe driver output is latched in the logic, preventing multiple switch-on.
7.3.4 Demagnetization (FBAUX pin)The system is always in quasi-resonant or discontinuous conduction mode. The internal
oscillator does not start a new primary stroke until the previous secondary stroke has
ended.
Demagnetization features a cycle-by-cycle output short-circuit protection by immediately
lowering the frequency (longer off-time), thereby reducing the power level.
Demagnetization recognition is suppressed during the first tsup(xfmr_ring) time (2 μs typ).
This suppression may be necessary at low output voltages and at start-up and in
applications where the transformer has a large leakage inductance.
If pin FBAUX is open-circuit or not connected, a fault condition is assumed and the
converter stops operating immediately. Operation restartsas soonas the fault conditionis
removed.
7.3.5 Flyback control / time-out (FBCTRL pin)The pin FBCTRL is connected to an internal voltage source of 3.5 V via an internal
resistor (typical resistanceis3 kΩ).As soonas the voltageon this pinis above 2.5V (typ),
this connection is disabled. Above 2.5 V the pin is biased with a small current. When the
voltage on this pin rises above 4.5 V (typ), a fault is assumed and switching is inhibited.
When a small capacitor is connected to this pin, a time-out function can be created to
protect againstan open control loop situation (see Figure11 and Figure 12). The time-out
function can be disabled by connecting a resistor (100 kΩ) to ground on the FBCTRL pin.
If the pin is shorted to ground, switching of the flyback controller is inhibited.
In normal operating conditions, when the converter is regulating the output voltage, the
voltage on the FBCTRL pin is between 1.4 V and 2.0 V (typical values) from minimum to
maximum output power.
