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TDA9210
150 MHz PIXEL VIDEO CONTROLLER FOR MONITORS
Version 3.1
March 2000 1/19
TDA9210150 MHz PIXEL VIDEO CONTROLLER FOR MONITORS
PRELIMINARY DATA
FEATURE 150 MHZ PIXEL RATE 2.7ns RISE AND FALL TIMEI2C BUS CONTROLLED GREY SCALE TRACKING VERSUS BRIGHT-
NESS OSD MIXING NEGATIVE FEED-BACK FOR DC COUPLING
APPLICATION BEAM CURRENT ATTENUATION (ABL) PEDESTRAL CLAMPING ON OUTPUT
STAGE POSSIBILITY OF LIGHT OR DARK GREY
OSD BACKGROUND OSD INDEPENDENT CONTRAST CONTROL ADJUSTABLE BANDWIDTH INPUT BLACK LEVEL CLAMPING WITH
BUILT-IN CLAMPING PULSE STAND-BY MODE 5V TO8V POWER SUPPLY SYNC CLIPPING FUNCTION (SOG)
DESCRIPTIONThe TDA9210is anI2C Bus controlled RGB pre-
amplifier designedfor Monitor applications, ableto
mix the RGB signals coming from any OSD de-
vice. The usual Contrast, Brightness, Drive and
Cut-Off Controls are provided. addition,it includes the following features: OSD contrast, Bandwidth adjustment, Grey background, Internal back porch clamping pulse generator.
The RGB incoming signals are amplified and
shapedto drive any commonly used video amplifi-
ers without intermediate follower stages. Even
though encapsulatedina 24-pin package only,
thisIC allows any kindof CRT Cathode coupling: AC coupling with DC restore, DC coupling with Feed-back from Cathodes, DC coupling with Cut-Off controlsof the Video
amplifier (ST Amplifiers TDA9533/9530).for any ST Video pre-amplifier, the TDA9210is
ableto drivea real load without any external inter-
face.
Oneof the main advantagesof ST devicesis their
abilityto sink and source currents while mostof
the devices from our competitors have problems sink large currents.
These driving capabilities combined withan origi-
nal output stage structure suppress any static cur-
renton the output pins and therefore reduce dra-
matically the power dissipationof the device.
Extensive integration combined with high perform-
ance and advanced features make the TDA9210
oneof the best choice for any CRT Monitorin the
14”to 17” range.
Perfectly matched with the ST Video Amplifiers
TDA9535/36, these2 products offera complete
solution for high performance and cost-optimized
Video Board Application.
DIP20(Plastic Package)
ORDER CODE: TDA9210
TDA92102/19
- PIN CONNECTIONS- PIN DESCRIPTION
Pin Number Symbol Description IN1 Red Video Input ABL ABL Input IN2 Green Video Input GNDL Logic Ground IN3 Blue Video Input GNDA Analog Ground
7VCCA Analog VCC (5V) OSD1 Red OSD Input OSD2 Green OSD Input OSD3 Blue OSD Input FBLK Fast Blanking SCL SCL SDA SDA OUT3 Blue Video Output GNDP Power Ground OUT2 Green Video Output VCCP Power VCC(5Vto8V) OUT1 Red Video Output HSYNC/BPCP HSYNC/BPCP BLK Blanking Input
BLKIN1
ABL
IN2
GNDL
IN3
GNDA
VCCA
OSD1
OSD2
OSD3 FBLK
HSYNCor BPCP
OUT1
VCCP
OUT2
GNDP
OUT3
SDA
SCL 11
TDA92103/19
- BLOCK DIAGRAM- FUNCTIONAL DESCRIPTION
4.1- RGB InputThe three RGB inputs havetobe supplied through
coupling capacitors (100 nF).
The maximum input peak-to-peak video amplitude1V.
The input stage includesa clamping function. The
clamp uses the input serial capacitorasa ”memo- capacitor”. avoida dischargeof the serial capacitor during
the line (dueto leakage current), the input voltage referencedto the ground.
The clampis gated by an internally generated
”Back Porch Clamping Pulse” (BPCP). Register8
allowsto choose the wayto generate this BPCP
(see Figure 1).
Whenbit0is setto0, the BPCPis synchronized the trailingor leading edgeof HSYNC (Pin 19)
(bit1=0: trailing edge,bit1=1: leading edge).
BLK FBLK VCCP
OUT1
GNDP
OUT2
OUT3
IN1
IN2
IN3
ABL
GNDL
GNDA
VCCA
HSYNC SDA SCL OSD1 OSD2 OSD3 BPCP
TDA92101120 13 12 8 9 10
Output Clamp Pulse
(OCL)
Output
Stage
DriveContrast
VREF
Clamp
Green Channel
Blue Channel
Contrast/8bit
Latches2C
Bus
Decoder
D/A
BPCP
OSD
Cont.
4bits
Drive
3x8bits
Brightness
8bits
VREF
Output Level
4bitsI C
Cut-off
8bits
See Figure8for complete BPCP and OCL generation diagram
TDA92104/19
Additionally, theIC automatically works with either
positiveor negative HSYNC pulses. Whenbit0is setto1, BPCPis synchronizedon
the leading edgeof the blanking pulse BLK
(Pin 20). One can usea positiveor negative
blanking pulseby programmingbit0in
Register9 (SeeI2C Table 3). BPCP width canbe adjusted withbit2 and3 (see
Register8,I2C table 2).If the application already provides the Back
Porch Clamping Pulse,bit4 mustbe setto1
(providinga direct connection between Pin19
and internal BPCP).
4.2- Synchro Clipping FunctionThis functionis available on channel2 (Green
Channel). When using the Sync On Green (SOG)
(Synchro pulse includedin the green channel in-
put) the synchro clipping function mustbe activat- (bit7 setto1in register9)in orderto keep the
right green output levels and avoid unbalanced
colours.
4.3- Blanking InputThe Blanking pin (FBLK)is TTL compatible.
The Blanking pulse can be: positiveor negative lineor Composite-type (but not Frame-type).
4.4- Contrast Adjustment(8 bits)The contrast adjustmentis madeby controllingsi-
multaneously the gainof the three internal amplifi-
ers through theI2C bus interface. Register1 al-
lows the adjustmentina rangeof48 dB.
Figure1.
4.5- ABL ControlThe TDA9210 includes an ABL (automatic beam
limitation) inputto attenuate the RGB Video sig-
nals dependingon the beam intensity.
The operating rangeis2V (from3Vto1 V).A typ-
ical15 dB maximum attenuationis appliedto the
output signal whatever the contrast adjustmentis.
(See Figure2).
When the ABL featureis not used, the ABL input
(Pin2) mustbe connectedtoa5V supplyvoltage.
R8b0=0 and R8b1=0HSYNC/BPCP (Pin19)
Internal BPCP
R8b0=0 and R8b1=1HSYNC/BPCP (Pin19)
Internal BPCP
R8b0=1BLK (Pin20)
Internal BPCP
R8b4=1 HSYNC/BPCP (Pin19)
Internal BPCP
TDA92105/19
Figure2.
4.6- Brightness Adjustment(8 bits)
Brightness adjustmentis controlledby theI2C Bus
via Register2.It consistsof adding the same DC
voltageto the three RGB signals, after contrast ad-
justment. When the blanking pulse equals0, the voltageis settoa value which canbe adjusted
between0 and 2V with 8mV steps (see Figure 3).
The DC output levelis forcedto the ”Infra Black”
level (VDC) when the blanking pulseis equalto1.
4.7- Drive Adjustment(3x8 bits) orderto adjust the white balance, the TDA9210
offers the possibilityof adjusting separately the
overall gainof each channel thanksto theI2C bus
(Registers3,4 and 5).
The very large drive adjustment range (48 dB)al-
lows different standardsor custom color tempera-
tures. can alsobe usedto adjust the output voltagesat
the optimum amplitudeto drive the CRT drivers,
keeping the whole contrast control for the end-
user only.
The drive adjustmentis located after the Contrast,
Brightness and OSD switch blocks,soit does not
affect the white balance setting when the BRTis
adjusted.It also operates on the OSD portionof
the signal.
4.8- OSD InputsThe TDA9210 allowsto mix the OSD signals into
the RGB main picture. The four pins dedicatedto
this function are the following: ThreeTTL RGB inputs (Pins8,9, 10) connected the three outputsof the corresponding OSD
processor. One TTL fast blanking input (Pin 11) also con-
nectedto the FBLK outputof the OSDprocessor.
Whena high levelis present on the FBLK, theIC
actsas follows: The three main picture RGB input signals (IN1,
IN2, IN3) are internally switchedto the internal
input clamp reference voltage. The three output signals are setto the voltage
correspondingto the three OSD input logic
states(0or 1). (See Figure3). the OSD inputisat low level, the output and
brightness voltages (VBRT) are equal. the OSD inputisat high level, the output voltage VOSD, where VOSD =VBRT+ OSD and OSDisI2C bus-controlled voltage.
OSD varies between0Vto 4.9Vby 320 mV steps
via Register7(4 bits). The same variationis ap-
plied simultaneouslyto the three channels provid-
ing the OSD contrast.
The grey color can be obtainedon output signals
when: OSD1=1, OSD2=0 and OSD3=1,A specialbit (bit5or6)in Register9is setto1. R9b5is setto1, light greyis obtainedon output. R9b6is setto1, dark greyis obtainedon output. the case where R9b5 and R9b6 are setto0, the
normal operationis providedon output signals.
4.9- Output StageThe overall waveformsof the output signal are
shownin Figure3 and Figure4. The three output
stages, which are large bandwidth output amplifi-
ers, are ableto deliverupto 4.4VPPfor 0.7VPPon
input.
Whena high levelis applied on the BLK input
(Pin 20), the three outputs are forcedto ”Infra
Black” level (VDC) thankstoa sample and hold cir-
cuit (described below).
The black level (whichis the output voltage out-
side the blanking pulse with minimum brightness
andno Video input signals)is 400 mV higher than
VDC.
The brightness level(V BRT)is then obtained by
programming register2 (seeI2C table1).
The sample and hold circuitis usedto control the
”Infra Black” levelin the rangeof 0.5Vto 2.5V via
Register6 (in caseof AC coupling)or Registers
10, 11, 12(in caseof DC coupling).
This sampling occurs during an internal pulse
(OCL) generated inside the blanking pulse win-
dow.
Referto “CRT cathode coupling” part for further
details.
Attenuation (dB)ABL (V)321
TDA92106/19
Functioning with5V PowerVCC simplify the application,itis possibleto supply
the powerVCC with5V (insteadof8V nominal)at
the expenseof output swing voltage.
Functioning without Blanking Pulseno blanking pulseis appliedto the TDA9210, the
internal BPCP can be connectedto the sample
and hold circuit (Register8,bit7=1 and BLK pin
grounded)so that the output DC levelis still con-
trolledbyI2C. ensure the device correct behaviorin the worst
possible conditions, the Brightness Register must setto0.
Figure3. Waveforms VOUT, BRT, CONT, OSDNotes: VDC = 0.5to 2.5V VBLACK = VDC+ 0.4V VBRT = VBLACK+ BRT (with BRT=0to 2V) VCONT = VBRT+ CONT=kx VideoIN (CONT= 4.4VPP max.for VIN= 0.7VPP) VOSD = VBRT+ OSD (OSD max.= 4.9VPP, OSD min= 0VPP)
HSYNC
BPCP
BLK
VideoIN
FBLK
OSDINDC
CONT
BRT
0.4V fixed CONT
(4) OSD
(5)BRT
(3) BLACK
(2)
(1)
OSD
VOUT1, VOUT2 ,VOUT3
TDA92107/19
Figure4. Waveforms (Drive adjustment)
4.10- Bandwidth Adjustment new feature: Bandwidth adjustment, has been
implementedon the TDA9210.
This function has several advantages: Dependingon the external capacitive load and the peak-to-peak output voltage, the band-
width canbe adjustedto avoid any slew-rate
phenomenon. The preamp bandwidth canbe adjustedin order reduce electromagnetic radiation, sinceitis
possibleto slow down the signal rise/fall timeat
the CRT driver input without too much affecting
the rise/fall timeat the CRT driver output.Itis possibleto optimize the ratioof the frequen- response versus the CRT driver power con-
sumptionfor any kindof chassis,as the preamp
bandwidth adjustment also allows the adjust-
mentof the rise/fall timeon the cathode (through
the CRT driver).In still picture mode, whena high Video swing
voltageisof greater interest than rise/fall time,
bandwidth adjustmentis usedto avoid any slew-
rate phenomenonat the CRT driver output andto
meet electromagnetic radiation requirements.
4.11- CRT Cathode Coupling (Figure5)
The TDA9210is designedto be usedin DC cou-
pling mode, enablingto builda powerful video sys-
temona small PCB Board and givinga substantial
cost saving compared with any other solution
availableon the market.
The preamplifier outputs control directly the cut-off
levels.
The output DC level (VDC)is adjusted independ-
entlyfor each channel from 0.5Vto 2.5V via reg-
isters 10, 11 and 12. DC coupling mode,bit2 must be setto1 and
bit3to0in Register9.
HSYNC
BPCP
BLK
VideoIN
BFLK
OSDIN CONT
Two examplesof drive
adjustment(1)
VBLACK
VDC
VBRT
VOSD
VOUT1,VOUT2,VOUT3
Note:
1.Drive adjustment modifies the following voltages: VCONT,VBRT and VOSD.
Drive adjustment doesn’t modify the following voltages: VDC andV BLACK.
TDA92108/19
Figure5. DC Coupling
4.12- Stand-by ModeThe TDA9210 hasa stand-by mode. As soonas
the VCC power (Pin 17) gets lower than 3V (typ.),
the deviceis setin stand-by mode whatever the
voltage on analogV CCA (Pin7) is. The analog
blocks are internally switched-off while the logic
parts(I2C bus, power-on reset) are still supplied. stand-by mode, the power consumptionis be-
low 20 mW.
4.13- Serial InterfaceThe 2-wire serial interfaceisanI2C interface. The
slave addressof TDA9210is DC hex.
The host MCU can write into the TDA9210 regis-
ters. Read modeis not available. orderto write data into the TDA9210, after the
“start” message, the MCU must send the following
data (see Figure6): theI2C address slave byte with alow level forthe
R/W bit, the byteto the internal register address where
the MCU wantsto write data, the data.
All bytes are sent with MSBbit first. The transferof
written datais ended witha “stop” message.
When transmitting several data, the register ad-
dresses and data can be written with no needto
repeat the start and slave addresses.
4.14- Power-on Reset power-on reset functionis implemented on the
TDA9210 so that theI2C registers havea deter-
mined status after power-on. The Power-on reset
threshold fora rising supply onV CCA (Pin7)is
3.8V (typ.) and 3.2V when the VCC decreases.
Figure6.I2C Write OperationOUTPUT 1,2,3 DC LEVEL
Pins 14-16-18
CRTCRT
Driver
TDA 92100.5Vto 2.5V (8bits)
A5 A4 A3 A2 A1 A0 W110 111 00
SCL A7 A6 A5 A4 A3 A2A1 A0
SDARegister Address ACKACKI2C SlaveAddressStart D6 D5 D4 D3 D2 D1 D0
DataByte ACK Stop
TDA92109/19
- ABSOLUTE MAXIMUM RATINGS- THERMAL DATA- DC ELECTRICAL CHARACTERISTICSTamb =25°C,V CCA =5V,V CCP= 8V, unless otherwise specified.
Symbol Parameter Pin Value UnitsVCCA Max.
VCCP Max.
Supply Voltageon Analog VCC
Supply Voltageon Power VCC
Vin Max. Voltageat any Input Pins (except Video inputs) and Input/Output Pins - 5.5 V Max. Voltageat Video Inputs 1,3,5 1.4 V
Tstg Storage Temperature - - °C
Toper Operating Junction Temperature - +150 °C
Symbol Parameter Value UnitsRth(j-a) Max. Junction-ambient Thermal Resistance 69 °C/W Typ. Junction Temperatureat Tamb =25°C80 °C
Symbol Parameter Test Conditions Min. Typ. Max. UnitsVCCA Analog Supply Voltage Pin7 4.5 5 5.5 V
VCCP Power Supply Voltage Pin17 4.5 8 8.8 V
ICCA Analog Supply Current VCCA =5V 70 mA
ICCP Power Supply Current VCCP =8V 55 mA Video Input Voltage Amplitude 0.7 1 V Output Voltage Range 0.5 VCCP
-0.5V VIL
VIH
Low Level Input Voltage
High Level Input Voltage
OSD, FBLK, BLK, HSYNC
0.8 V
IIN Input Current OSD, FBLK, BLK -1 1 μA
RHS Input Resistor HSYNC 40 kΩ
TDA921010/19
- AC ELECTRICAL CHARACTERISTICS
Note1: Assuming that VOM remains within the rangeofVo (between 0.5V and VCCP- 0.5V)
Note2: tR,tF are calculated values, assumingan ideal input rise/fall timeof 0ns(tR= ,tF=
Symbol Parameter Test Conditions Min. Typ. Max. Units
VIDEO INPUTS (PINS1,3,5) Video Input Voltage Amplitude Max. Contrast and Drive 0.7 1 V
VIDEO OUTPUT SIGNAL (PINS 14,16, 18)- GENERALGAM Maximum Gain Max Contrast and Drive
(CRT= DRV= 254 dec) dB
VOM Maximum Video Output Voltage
(Note1)
Max Contrast and Drive
(CRT= DRV= 254 dec)
4.4 V
VON Nominal Video Output Voltage Contrast and Driveat POR
(CRT= DRV= 180 dec)
2.2 V
CAR Contrast Attenuation Range From max.Contrast (CRT=254 dec) min. Contrast (CRT=1 dec) dB
DAR Drive Attenuation Range From Max. Drive (DRV= 254 dec) min Drive (DRV=1 dec) dB Gain Matching Contrast and Driveat POR ±0.1 dB
tR,tF Rise Time, Fall Time (Note2) VOUT =2 VPP (BW=15 dec)
VOUT =2 VPP (BW=0 dec)
4.3 Large Signal Bandwidth VOUT =2 VPP 130 MHz Bandwidth Adjustment Range VOUT =2VPP
Minimum bandwidth (BW=0 dec)
Maximum bandwidth (BW =15 dec)
MHz
MHz Crosstalk between Video Outputs VOUT =2 VPP @f=10 MHzf=50 MHz
VIDEO OUTPUT SIGNAL— BRIGHTNESSBRTmax Maximum Brightness Level Max. Brightness (BRT= 255 dec)
and Max. Drive (DRV= 254 dec)
BRTmin Minimum Brightness Level Min. Brightness (BRT=0 dec)
and Max. Drive (DRV= 254 dec)
VIP Insertion Pulse 0.4 V
BRTM Brightness Matching Brightness and Driveat POR ±10 mV
VIDEO OUTPUT SIGNAL— OSDOSDmax
OSDmin
Maximum OSD Output Level
Minimum OSD Output Level
Max. Drive (DRV= 254 dec)
Max. OSD (OSD=15 dec)
Min. OSD (OSD=0 dec)
VIDEO OUTPUT SIGNAL— DC LEVEL (DC COUPLING MODE)
DCLmax
DCLmin
Maximum OutputDC Level
Minimum Output DC Level
Max. Cut-off (Cut-off= 255 dec)
Min. Cut-off (Cut-off=40 dec)
DCLstep Output DC Level Step 10 mV
DCLTD Output DC Level Drift Tj variation=100°C 0.5 %
Tamb =25°C,V CCA =5V,V CCP =8V,Vi= 0.7VPP,C LOAD= 5pFS= 100Ω, serial between output pin andC LOAD, unless otherwise specified.
tROUT2 +tRIN2 tFOUT2 +tFIN2
