TDA9203A Fast Delivery |IC PHOENIX CO.,LIMITED

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TDA9203A
I2C BUS CONTROLLED 70MHz RGB PREAMPLIFIER
TDA9203A2C BUS CONTROLLED 70MHz RGB PREAMPLIFIER
June 1998
SHRINK24
(Plastic Package)
ORDER CODE: TDA9203A 70MHz TYPICAL BANDWIDTH AT 4VPP OUT-
PUT WITH 12pF CAPACITIVELOAD. 5.5ns TYPICAL RISE/FALL TIME AT 4VPP
OUTPUT WITH 12pF CAPACITIVE LOAD. POWERFULL OUTPUT DRIVE CAPABILITY. BRT, CONT, DRIVE, OUTPUT DC LEVEL,
OSD CONTRAST, BACK-PORCH CLAMPING
PULSE WIDTH AREI2C BUS CONTROLLED. INTERNAL BACK-PORCH CLAMPING
PULSE GENERATOR. OSD WHITE BALANCE TRACKING. INTERNAL OSD SWITCHES. BLANKINGAND FAST-BLANKINGINPUTS. VERY LARGE DRIVE ADJUSTMENT RANGE
(48dB). SEMI-TRANSPARENT BACKGROUND ON
OSD PICTURE. ABL CONTROL
DESCRIPTION
The TDA9203Aisa digitaly controlled wideband
video preamplifier intended for usein mid range
color monitor. All controls and adjustments are
digitaly performed thankstoI2C serial bus. Con-
trast, brightness and DC output levelof RGB sig-
nals are commonto the3 channels and drive
adjustmentis separatefor each channel.ThreeI2C
gain controlled OSD inputs can be switched with
RGB signalsusing fast blanking command.Clamp-
ingof RGB signalsis performedthankstoa flexible
integrated system. The white balance adjustment effectiveon brightness,video and OSD signals.
The TDA9203A works for application using ACor coupled CRT driver.
The ABL input providesa 12dB Max. attenuation the current contrast value according average
beam limitation voltage.
Becauseof its features and dueto component
saving the TDA9203A leadstoa very performant
and cost effective application.
HSYNC
PVCC1
OUT1
PGND1
PVCC2
OUT2
PGND2
PVCC3
OUT3
PGND3
BLK
FBLK
IN1
OSD1DD
IN2
OSD2
AGND
IN3
OSD3
ABL
LGND
SDA
SCL
PIN CONNECTIONS
1/13
Name Pin Type Function
IN1 1 I 1st Channel Main Picture Input
OSD1 2 I 1st Channel OSD Input
AVDD 3 I 12V Analog VDD
IN2 4 I 2nd Channel Main Picture Input
OSD2 5 I 2nd Channel OSD Input
AGND 6 I/O Analog Ground
IN3 7 I 3rd Channel Main Picture Input
OSD3 8 I 3rd Channel OSD Input
ABL 9 I ABL Input
LGND 10 I/O Logic Ground
SDA 11 I/O Serial DataLine
SCL 12 I Serial Clock Line
Name Pin Type Function
FBLK 13 I Fast Blanking Input
BLK 14 I Blanking Input
PGND3 15 I/O 3rd Channel Power Ground
OUT3 16 O 3rd Channel Output
PVCC3 17 I 3rd Channel Power VCC
PGND2 18 I/O 2nd Channel Power Ground
OUT2 19 O 2nd Channel Output
PVCC2 20 I 2nd Channel Power VCC
PGND1 21 I/O 1st Channel Power Ground
OUT1 22 O 1st Channel Output
PVCC1 23 I 1st Channel Power VCC
HSYNC 24 I Horizontal Synch Input
9203A
PIN DESCRIPTION 1214
CLAMP
VREF
AVDD
IN1
AGND
IN2
BRIGHTNESS
IN3
OUTPUT
STAGE
DRIVEbits
BPCP
PVCC1FBLKBLK
OUT1
PGND1
PVCC2
OUT2
PGND2
OUT3
PGND3
PVCC3ABL
LGND
I2C
BUS
DECODER
D/A
LATCHESBPCP
SCLSDAHSYNC
OSD
OSD1 OSD2 OSD3
GREEN CHANNEL
BLUECHANNEL2C
VREF
OUTPUT LEVEL
ADJUST
TDA9203A
CONTRAST
CONT
03A
BLOCK DIAGRAM
TDA9203A
2/13
BLK
HSYNC
BPCP
Internal pulse widthis controlled byI2C
03A
Figure1
FUNCTIONAL DESCRIPTION
Input Stage
TheR,G andB signals mustbe fedto the three
inputsthrough coupling capacitors (100nF).
The maximum input peak-to-peak video amplitude 1V.
The input stage includesa clamping function.This
clampis using the input serial capacitoras ”mem-
ory capacitor” andis gatedbyan internally gener-
ated ”Back-Porch-Clamping-Pulse (BPCP)”.
The synchronizationedgeof the BPCPis selected
accordingbit0of register R8.
When B0R8is setto1, the BPCPis synchronized
ontheleadingedgeof theblankingpulseBLKinputs
onPin14 (seeFigure1).B7R8allowsto usepositive negative blanking signalon Pin 14.At poweron
resetTDA9203Ause only positive blanking.
WhenB0R8is clearto0, theBPCPis synchronized
onthesecondedgeof the horizontal pulseHSYNC
inputson Pin 24. An automatic function allowsto
use positiveor negativehorizontalpulseon Pin24
(see Figure2). both case BPCP widthis adjustablebyI2C, B1
and B2of register R8 (see R8 TableP8).
Contrast Adjustment(8 bits)
The contrast adjustmentis made by controlling
simultaneously the gainof three internal variable
gain amplifiers through theI2C bus interface.
The contrast adjustment allowsto covera typical
rangeof 48dB.
ABL Control
The TDA9203AI2C preamplifier providesan ABL
input (automatic beam limitation)to attenuate
R,G,B video signals accordingto beam intensity.
The operating rangeis 2.5V typicaly, from 5.3Vto
2.8V.A typical 12dB Max. attenuationis appliedto
the signal whatever the current gainis. Referto
Figure3for ABL input attenuationrange. caseof softwarecontrol, the ABL input mustbe
pulledto AVDD througha resistorto limit power
consumption (see Figure 11).
ABL input voltage must not exceeed AVDD. Input
resistoris 10kΩ and equivalent schematic givenin
Figure 11.
HSYNC
BPCP
Internal pulse widthis controlledbyI2C
Figure2
Brightness Adjustment(8 bits) for the contrast adjustment, the brightnessis
controlledbyI2C.
The brightness function consiststo add the same offsetto the threeR, G,B signalsafter contrast
amplification. This DC-Offsetis present only out-
side the blanking pulse (see Figure4).
The DC output level during the blanking pulse,is
forcedto ”INFRA-BLACK” level (VDC).
DriveAdjustment(3x8 bits)
Inordertoadjustthe white balance, theTDA9203A
offersthepossibilityto adjustseparatelythe overall
gainof each complete video channel.The gainof
each channelis controlledbyI2C (8bits each).
The verylarge driveadjustment range(48dB)allows
differentstandardor custom color temperature. can alsobe usedto adjust the output voltagesat
the optimum amplitudeto drive the C.R.T drivers,
keepingthewholecontrastcontrolforend-useronly.
The drive adjustmentis located after the CON-
TRAST, BRIGHTNESSand OSD switchblocks,so
that the white balance will remains correct when
BRTis adjusted, and will alsobe correcton OSD
portionof the signal.
-14 123456789
Attenuation(dB)
VIN (V)
-0X
Figure3
TDA9203A
3/13
FUNCTIONAL DESCRIPTION (continued)
OSD Inputs
The TDA9203Aincludesall the circuitry necessary
tomix OSDsignalsintotheRGB main-picture.Four
pins are dedicatedto this functionas follow.
Three TTL RGB On Screen Display inputs (Pin2, and8). These three inputs are connectedto the
three outputsof the corresponding ON-SCREEN-
DISPLAYprocessor (ex: STV942x).
One Fast Blanking Input (FBLK, Pin 13) whichis
also connectedto the FBLK outputof the same
ON-SCREEN-DISPLAYprocessor.
Whena high levelis presenton FBLK, theIC will
actsas follow: The three main picture RGB input signals are
internally switchedto the internal input clamp
reference voltage. The three output signals are setto voltages cor-
respondingto the state(0or1)on the three OSD
inputs (see Figure4).
Example: FBLK=1 and OSD1, OSD2, OSD3)=1,0,1
respectively.
Then OUT1, OUT2, OUT3 will be equalto VOSD,
VBRT,VOSD,
where: VBRT =VBLACK+ BRT, VOSD =VBRT+ OSD
BRTis the brightness DC levelI2C adjustable.
OSDis the On-Screen Display signal valueI2C
adjustablefrom 0Vto 5.5VPPby stepof 0.36V.
Semi-transparent functionis controlled thanksto
Bit6ofR8 register (see Table1).
When semi-transparent modeis activated, video
signalis dividedby2 (CONT).
Table1
FBLK OSD1 OSD2 OSD3 B6R8 Output
Signal (OUTn) x x x 0 Video x x x 0 OSD(1) x x x 1 Video 0 x x 1 OSD 1x 1 OSD xx0 1 OSD 1 0 1 1 Semi-trans-
parent(2)
Notes:1.All OSD colorsare displayed. One OSD coloris displayedas semi-transparent video
withouteffecton brightnessandDC level adjustment.
Output Stage
The threeoutputstagesincorporate threefunctions
which are: The blanking stage: When high levelis applied the BLK input (Pin 14), the three outputs are
switchedto avoltagewhichis 400mV lowerthan
the BLACK level. The black levelis the output
voltage with minimumbrightness when input sig-
nal video amplitudeis equalto ”0”. The output stage itself:Itisa large bandwidth
output amplifier which allowto deliverupto 5VPP the three outputs(for 0.7V video signalon the
inputs). The output CLAMP: TheIC also incorporates
three internal output clamp (sample and hold
system) which allowto DC shift the three output
signals. The DC output voltageis adjustable
throughI2C with4 bits. Practicaly, the DC output
level allowto adjust the BLKlevel (VDC= 400mV
underVBLACK) from 0.9Vto 2.9Vwith12 x165mV.
The overall waveformsof the output signalaccord-
ingto the different adjustment are shownin Fig-
ures4 and5.
Serial Interface
The 2-wires serial interfaceisanI2C interface.
The slave addressof the TDA9203Ais DC (in
hexadecimal). A5 A4 A3 A2 A1 A0 W
110 111 00
Data Transfer
The host MCU can write data into the TDA9203A
registers. Read modeis not available. write data into the TDA9203A, aftera start, the
MCU must send (see Figure6): TheI2C addressslavebyte witha lowlevelfor the
R/W bit. The byteof the internal register address where
the MCU wantsto write data(s). The data.
All bytes are sent MSBbit first and the write data
transteris closedbya stop.
TDA9203A
4/13
HSYNC
VCONT(4)
BPCP
BLK
VideoIN
FBLK
OSDIN
VOSD(5)
VBRT(3)
VBLACK(2)
VDC(1)
CONTOSD
BRT
0.4V fixed
VOUT1,VOUT2,VOUT3
Notes:1. VDC= 0.5to 2.5V VBLACK =VDC+ 0.4V VBRT =VBLACK +BRT (withBRT=0 to2.5V) VCONT=VBRT+ CONTwith CONT=kx VideoIN (CONT=5VPP max.forVIN= 0.7VPP) VOSD =VBRT+ OSDwithOSD=k1 xOSDIN (OSD max. =5.5VPP, OSDmin.= 360mVPP)
Figure4: WaveformsVOUT, BRT, CONT, OSD
HSYNC
VCONT
BPCP
BLK
VideoIN
FBLK
OSDIN
VOSD
VBRT
VBLACK
VDC
VOUT1,VOUT2,VOUT3
Note:1. Drive adjustment modifiesthe following voltages: VCONT,VBRTand VOSD.
Drive adjustment donotmodify thefollowing voltages:VDCand VBLACK.
Two exemples drive adjustment(1)
Figure5: Waveforms(DRIVE adjustment)
FUNCTIONAL DESCRIPTION (continued)
SCL A7 A6 A5A4 A3 A2A1 A0SDA
RegisterAddress ACKACKI2CSlave AddressStart D6 D5D4 D3D2 D1 D0
DataByte ACK Stop
9203A
8.E
Figure6:I2C Write Operation
TDA9203A
5/13
QUICK REFERENCE DATA
Symbol Parameter Min. Typ. Max. Unit
Signal Bandwidth (4VPP/12pF load) 70 MHz
Rise and Fall Time (4VPP/12pF load) 5.5 ns
Drive Adjustment Rangeon the3 Channels separately 48 dB
Maximum Output Voltage (VIN=0.7 VPP)5 VPP
Output Voltage Range (AC+ DC) 8 V
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit Supply Voltage (Pins 3-9-17-20-23) 14 V
VIN1 Voltageat any Input Pins (except SDA& SCL& Logical Inputs) GND< VIN1 VIN2 Voltageat Input Pins SDA& SCL GND< VIN2< 5.5 V
VIN3 Voltageat Logical Inputs (OSD, FBLK, BLK, HSYNC) GND< VIN3< 5.5 V
VESD ESD Susceptability (Human body model; 100pF Discharge through 1.5kΩ)2 kV
Tstg Storage Temperature -40,+ 150 °C Junction Temperature 150 °C
Toper Operating Temperature 0,+70 °C
THERMAL DATA
Symbol Parameter Value Unit
Rth(j-a) Junction-ambient Thermal Resistance 69 o C/W
-04. ELECTRICAL CHARACTERISTICS (Tamb =25oC, VCC= 12V,unless otherwise specified)
Symbol Parameter Test Conditions Min. Typ. Max. Unit Supply Voltage Pins 3-9-17-20-23 10.8 12 13.2 V Supply Current (AllVS Pin current) RL =1kΩ 60 mA Video Input Voltage Amplitude Pins 1-4-7 0.7 1 VPP Typical Output Voltage Range Pins 16-19-22 0.5 - 8 V
VIL Low Level Input (OSD, FBLK, BLK, HSYNC) Pins 2-5-8-13-14-24 0.8 V
VIH High Level Input (OSD, FBLK, BLK, HSYNC) Pins 2-5-8-13-14-24 2.4 V
IIN Input Current (OSD, FBLK, BLK, HSYNC) 0.4V< VIN< 4.5V -10 +10 μA
5.T
TDA9203A
6/13
ELECTRICAL CHARACTERISTICS(Tamb =25oC, VCC= 12V,CL= 12pF,RL =1kΩ , unless otherwise specified)
Symbol Parameter Test Conditions Min. Typ. Max. Unit Maximum Gain(20logx VOUT AC/VINAC) Contrast& Driveat maximum 18 dB
CAR Contrast Attenuation Range VIN= 0.7VPP, Contrast& Driveat POR 48 dB
DAR Drive AttenuationRange 48 dB Gain Match VOUT= 2.5VPP,VIN= 0.7VPP
Contrast= Drive= Maxix0.7
(power-on reset value) 0.1 dB Bandwidth Large Signal At -3dB, VIN= 0.7VPP,VOUT =4VPP
Contrast= Drive= Maxix 0.87 MHz
DIS Video Output Distorsion (see Note) f= 1MHz, VOUT =1VPP,VIN =1VPP 0.3 %
tR,tF Video Output Rise and Fall Time
(see Note)
VIN= 0.7VPP,VOUT =4VPP
Contrast= Drive= Maxix 0.87
5.5 ns
BRT Brightness Maximum DC Level
Brightness MinimumDC Level
BRTM Brightness Matching BRT= 50%, Driveat POR ±20 mV
OSD
CAR
Contrast Attenuation Range
for OSD Input dB Output Maximum DC Level
Output Minimum DC Level
0.5 Equivalent Loadon Video Output withTj≤Tj Max. 1kΩ Croostalk between Video Channels
(see Note)
VOUT= 2.5VPP,VIN= 0.7VPP
Contrast= Drive= Maxix0.7
(power-on reset value)
fIN= 1MHz dB
GABL ABL Min. Attenuation
ABL Max. Attenuation
VABL= 5.3V Typical
VABL= 2.8V Typical
IABL ABL Input Current VABL= 5.3V 20 μA
RABL ABL Input Resistor See Figure11 10 kΩ
Note: These parametersarenot testedon each unit. They are measured duringan internal qualification procedure which includes
characterizationon batches coming from cornersofour processesand also from temperature characterization.
-06.2C ELECTRICAL CHARACTERISTICS (Tamb =25oC, VCC= 12V,unless otherwise specified)
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VIL Low Level Input Voltage On Pins SDA, SCL 1.5 V
VIH High Level Input Voltage 3 V
IIN Input Current (Pins SDA, SCL) 0.4VfSCL(Max.) SCL Maximum Clock Frequency 200 kHz
VOL Low Level Output Voltage SDA Pin when ACK
Sink Current= 6mA
0.6 V
TDA9203A
7/13

Partno	Mfg	Dc	Qty	Available	Descript
TDA9203A	STM	N/a	120	avai	I 2 C BUS CONTROLLED 70MHz RGB PREAMPLIFIER