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TDA9110-TDA9110.
LOW-COST DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
TDA9110LOW-COST DEFLECTION PROCESSOR
FOR MULTISYNC MONITORS
December 1997
PRODUCT PREVIEWSDA
SCL
VCC
GND
HOUT
XRAY
EWOUT
VOUT
VCAP
VREF
VAGCCAP
VGND
DCBREATH
GND
HREF
HFLY
HGND
HFOCUSCAP
FC1
PLL2C
HLOCKOUT
HMOIRE
H/HVIN
VSYNC-IN
PLL1F
HPOS
HLOCKCAP
HVFOCUS
HSIZE
PIN CONNECTIONS
SHRINK32
(Plastic Package)
ORDER CODE: TDA9110
HORIZONTAL. EXTREMELY LOW JITTER LEVEL. SELF-ADAPTATIVE. DUAL PLL CONCEPT. 150kHz MAXIMUM FREQUENCY. X-RAYPROTECTION INPUT.I2C CONTROLS: HORIZONTAL DUTY-CYCLE,
H-POSITION
VERTICAL. VERTICAL RAMP GENERATOR.50 TO 165Hz AGC LOOP. GEOMETRY TRACKINGWITH V-POS& AMP.I2C CONTROLS:
V-AMP, V-POS, S-CORR, C-CORR. DC BREATHINGCOMPENSATION
2
C GEOMETRYCORRECTIONS. VERTICAL PARABOLA GENERATOR
(Pincushion, Keystone). HORIZONTAL SIZE CONTROL (Amplitude). HORIZONTAL DYNAMIC PHASE
(Side Pin Balance& Parallelogram). HORIZONTAL AND VERTICAL DYNAMIC FO-
CUS (Horizontal Focus Amplitude, Horizontal
Focus Symmetry, Vertical Focus Amplitude)
GENERAL. SYNCHRO PROCESSOR. 12V SUPPLY VOLTAGE.8V REFERENCE VOLTAGE. HOR.& VERT. LOCK UNLOCK OUTPUTS. READ/WRITEI2C INTERFACE. HORIZONTAL AND VERTICAL MOIRE
DESCRIPTIONThe TDA9110isa monolithic integrated circuit as-
sembledin 32-pin shrunk dualin line plastic pack-
age. ThisIC controlsall thefunctions relatedto the
horizontal and vertical deflectionin multimodeor
multi-frequency computer display monitors.
The internal synchro processor, combined with the
very powerful geometry correction block make the
TDA9110 suitablefor very high performancemoni-
tors with very few externalcomponents.
The horizontal jitter levelis extremelylow. (Typical
standard deviation: 300ps@ 31kHz).is particularly wellsuitedfor high-end15” and 17”
monitors.
Combined with ST7275 Microcontroller family,
TDA9206 (Video preamplifier) and STV942x
(On-Screen Display controller) the TDA9110
allowsto built fullyI2C bus controlled computer
display monitors, witha reduce numberof ex-
ternal components.
1/29
PIN CONNECTIONS
Pin Name Function H/HVIN TTL compatible Horizontal Synchro Input VSYNCIN TTL compatible Vertical Synchro Input (for separated H&V) HMOIRE Horizontal Moire Output(tobe connectedto PLL2C througha resistor divider) HLOCKOUT First PLL Lock/Unlock Output (0V unlocked-5V locked) PLL2C Second PLL LoopFilter FC1 High Threshold VCO Decoupling Filter C0 Horizontal Oscillator Capacitor R0 Horizontal Oscillator Resistor PLL1F First PLL Loop Filter HPOS Horizontal Position Decoupling Filter HGND Horizontal Section Ground HFLY Horizontal Flyback Input (positive polarity) HREF Horizontal Section Reference Voltage(tobe filtered) HLOCKCAP First PLL Lock/Unlock Time Constant Capacitor FOCUSOUT Mixed Horizontal and Vertical Dynamic Focus Output HFOCUSCAP Horizontal Dynamic Focus Oscillator Capacitor GND Ground (related internal reference) BREATH DC Breathing Input Control VGND Vertical Section Ground VAGCCAP Memory Capacitorfor Automatic Gain Control Loopin Vertical Ramp Generator VREF Vertical Section Reference Voltage(tobe filtered) VCAP Vertical Sawtooth Generator Capacitor VOUT Vertical Ramp Output (withfrequency independant amplitude andSorC Correctionsif any).is mixed with vertical position reference voltageoutput and vertical moire. EWOUT East/West PincushionCorrection Parabola Output XRAY X-RAY protection input (with internal latch function) HOUT Horizontal Drive Output (int. trans. open collector) GND General Ground (referencedto VCC) HSIZE DC HSize Control Output VCC Supply Voltage (12V Typ) SCL I2C Clock Input SDA I2C Data Input 5V Supply Voltage (5V Typ.)
TDA9110
2/29
QUICK REFERENCE DATA
Parameter Value UnitHorizontal Frequency 15to 150 kHz
Autosynch Frequency (for givenR0 and C0) 1to 4.5F0 Horizontal Synchro Polarity Input YES
Polarity Detection (on bothHorizontal and Vertical Sections) YES
TTL Composite Synchro YES
Lock/Unlock Identification(on both Horizontal1st PLL and Vertical Section) YES2C Controlfor H-Position ±10 %
XRay Protection YES2C Horizontal Duty Adjust 30to60 %2C Free Running Adjustment NO
Stand-by Function YES
Two Polarities H-Drive Outputs NO
Supply Voltage Monitoring YES
PLL1 Inhibition Possibility NO
Horizontal Blanking Output YES
Vertical Frequency 35to 200 Hz
Vertical Autosync (for 150nF) 50to 150 Hz
Vertical S-Correction YES
Vertical C-Correction YES
Vertical Amplitude Adjustment YES Breathing Controlon Vertical Amplitude YES
Vertical Position Adjustment YES
East/West Parabola Output YES
Pin Cushion Correction Amplitude Adjustment YES
Keystone Adjustment YES
Internal Dynamic Horizontal Phase Control YES
Side Pin Balance Amplitude Adjustment YES
Parallelogram Adjustment YES
Trackingof Geometric Corrections YES
Reference Voltage (bothon Horizontal and Vertical) YES
Dynamic Focus (both Horizontal and Vertical) YES2C Horizontal Dynamic Focus Amplitude Adjustment YES2C Horizontal Dynamic Focus KeystoneAdjustment YES2C Vertical Dynamic Focus Amplitude Adjustment YES
Typeof Input Synchro Detection (suppliedby 5VDigital Supply) YES
Vertical Moiré Output YES2C Controlled V-Moiré Amplitude YES
Frequency Generatorfor Burn-in NO
FastI2C Read/Write 400 kHz
Horizontal Moiré Output YES2C controlled H-Moiré Amplitude YES HSize Output Amplitude Control YES
TDA9110
3/29
VMOIRE
bits
POS
Amp
(7bits)
Kest
bits)
HFOCUSCAP
REF 11
HREF
HGND
SYNC
PROCESSOR
SYNC
INPUT
SELECT
bit)
LOCK/UNLOCK
IDENTIFICATION
PHASE
COMPARATOR
PHASE
SHIFTER
H-DUTY
bits)
HOUT
BUFFER
PHASE/FREQUENCY
COMPARATOR
H-PHASE
bits)
VCO
VAMP
bits 31 27
SDA
SCL
GND 19
VREF
VGND
REF
AND
CORRECTION
VERTICAL
OSCILLATOR
RAMP
GENERATOR
GEOMETRY
TRACKING
bits
bits
Keyst.
bits
PCC7
bits
TDA9110LL1F
LOCKOU
LOCKCA
FLY
LL2C
OUT
CAP
AGCCAP
OUT
VSYNCIN
H/HVIN
EWO29
XRAYV
RESET
GENERATOR
INTERFACE
VPOS
bits
VFOCUS
bits
HVFOCUS
Key
Bal
bits
Spin
Bal
bits
SAFETY
PROCESSOR
XRAYV
DCBRE
ATH
GND
bits
HFLYVSYNC
HMOIRE
bits
HSIZE
BLOCK DIAGRAM
TDA9110
4/29
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value UnitVCC Supply Voltage (Pin 29) 13.5 V
VDD Supply Voltage (Pin 32) 5.7 V
VIN Max Voltageon Pin12
Pin5
Pin16
Pin7
Pins8,9,14, 20,22
Pin15, 18,23, 24,25, 26,28
Pins1,2,3,4,30,31
VCC
VDD
VESD ESD susceptibility Human Body Model,100pF Discharge through 1.5kΩ
EIAJ Norm,200pF Discharge through0Ω
HSize Cur Max. Sourced Current (Pin28)
Max. Sunk Current (Pin 28)
Tstg Storage Temperature -40, +150 oC Junction Temperature +150 oC
Toper Operating Temperature 0, +70 oC
THERMAL DATA
Symbol Parameter Value Unit
Rth(j-a) Junction-ambient Thermal Resistance Max. 65 o C/W
SYNCHRO PROCESSOR
Operating Conditions (VDD =5V,Tamb =25oC)
Symbol Parameter Test Conditions Min. Typ. Max. UnitHsVR Horizontal Synchro Input Voltage Pin1 0 5 V
MinD Minimum Horizontal Input Pulses Duration Pin1 0.7 μs
Mduty Maximum HorizontalInput Signal Duty Cycle Pin1 25 %
VsVR Vertical Synchro Input Voltage Pin2 0 5 V
VSW Minimum Vertical Synchro Pulse Width Pin2 5 μs
VSmD Maximum VerticalSynchro Input Duty Cycle Pin2 15 %
VextM Maximum VerticalSynchro Width onTTL H/Vcomposite Pin1 750 μs
Electrical Characteristics(VDD =5V, Tamb =25oC)
Symbol Parameter Test Conditions Min. Typ. Max. UnitVINTH Horizontal and Vertical Input Threshold Voltage
(Pins1,2)
Low Level
High Level 2.2
0.8 V
RIN Horizontal and Vertical Pull-Up Resistor Pins1,2 200 kΩ
VOut Output Voltage (Pin4) Low level
High Level
TfrOut Falling and Rising Output CMOS Buffer Pin4, Cout= 20pF 200 ns
VHlock Horizontal1st PLL Lock Output Status (Pin4) Locked
Unlocked
VoutT Extracted Vsync Integration Time (%of TH)on H/V
Composite= 820pF 26 35 %
2
C READ/WRITE
Electrical Characteristics(VDD =5V,Tamb =25oC)
Symbol Parameter Test Conditions Min. Typ. Max. Unit2C PROCESSOR
Fscl Maximum Clock Frequency Pin30 400 kHz
Tlow Low periodofthe SCL Clock Pin30 1.3 μs
Thigh High periodofthe SCL Clock Pin30 0.6 μs
Vinth SDA and SCL Input Threshold Pins 30,31 2.2 V
VACK Acknowledge Output Voltage onSDA input with 3mA Pin31 0.4 V
SeealsoI2 CTable ControlandI2C Sub AddressControl
TDA9110
5/29
HORIZONTAL SECTION
Operating Conditions
Symbol Parameter Test Conditions Min. Typ. Max. UnitVCO
R0(Min.) Minimum Oscillator Resistor Pin8 4 kΩ
C0(Min.) Minimum Oscillator Capacitor Pin7 390 pF
F(Max.) Maximum Oscillator Frequency 150 kHz
OUTPUT SECTION
I12m Maximum Input Peak Current Pin12 2 mA
HOI Horizontal Drive Output Maximum Current Pin26, Sunk
current mA
Electrical Characteristics(VCC= 12V,Tamb =25oC)
Symbol Parameter Test Conditions Min. Typ. Max. UnitSUPPLY AND REFERENCE VOLTAGES
VCC Supply Voltage Pin29 10.8 12 13.2 V
VDD Supply Voltage Pin32 4.5 5 5.5 V
ICC Supply Current Pin29 50 mA
IDD Supply Current Pin32 5 mA
VREF-H Horizontal Reference Voltage Pin13,I= 5mA 7.4 8 8.6 V
VREF-V Vertical Reference Voltage Pin21,I= 5mA 7.4 8 8.6 V
IREF-H Max. Sourced Currenton VREF-H Pin13 5 mA
IREF-V Max. Sourced Currenton VREF-V Pin21 5 mA
1st PLL SECTION
HpolT Polarity Integration Delay 0.75 ms
VVCO VCO Control Voltage (Pin9) VREF-H =8V
fH(Max.)
VREF-H/6
Vcog VCO Gain (Pin9) R0= 5.9kΩ,C0= 820pF,
dF/dV= 1/11R0C0
18.8 kHz
Hph Horizontal Phase Adjustment %of Horizontal Period ±10 %
Hphmin
Hphtyp
Hphmax
Horizontal Phase Setting Value
Minimum Value
Typical Value
Maximum Value
Sub-Address01
Byte x1111111
Byte x1000000
Byte x0000000
3.8 Free Running Frequency R0= 5.9kΩ,C0= 820pF,= 0.97/8R0C0 kHz
dF0/dT Free Running Frequency Thermal Drift
(No drifton external components)
See Note -150 ppm/C PLL1 Capture Range R0= 6.49kΩ,C0= 820pF,
from f0+0.5kHzto 4.5F0
fH(Min.)
fH(Max.)
Component accuracy:= 2%,R0 =1%
100 kHz
kHz
Note: This parameterisnot testedon eachunit.Itis measured duringour internal qualification.
TDA9110
6/29
HORIZONTAL SECTION (continued)
Electrical Characteristics(VCC= 12V,Tamb =25oC) (continued)
Symbol Parameter Test Conditions Min. Typ. Max. Unit2nd PLL SECTION AND HORIZONTAL OUTPUT SECTION
FBth Flyback Input Threshold Voltage (Pin 12) 0.65 0.75 V
Hjit Horizontal Jitter Horizontal Freq.= 31kHz 60 ppm
HDmin
HDmax
Horizontal Drive Output Duty-Cycle
(Pin 26) (see Notes1&2)
Low Level
High Level
Sub-Address00
Byte xxx11111
Byte xxx00000
XRAYth X-RAY Protection Input Threshold Voltage Pin25 8 V
Vphi2 Internal Clamping Levelson 2nd PLL Loop
Filter (Pin5)
Low Level
High Level
VSCinh Threshold VoltageTo Stop H-Out,V-Out
when VCC< VSCinh
Pin29 7.5 V
HDvd Horizontal Drive Output (low level) Pin26 IOUT= 30mA 0.4 V
HORIZONTAL DYNAMIC FOCUS FUNCTION
HDFst Horizontal Dynamic Focus Sawtooth
Minimum Level
Maximum Level
HfocusCap=C0= 820pF,
TH=TBD, Pin16 2
HDFdis Horizontal Dynamic Focus Sawtooth
Discharge Width
Startby HDFstart 400 ns
HDFstart Internal fixed Phase Advance versus Hfly
Middle
Fixedfor each frequency
(Pin16)
860 ns
HDFDC Bottom DC OutputLevel RLOAD= 10kΩ, Pin15 2 V
TDHDF DC Output Voltage Thermal Drift 200 ppm/C
HDFamp Horizontal Dynamic Focus Amplitude
Min Byte x1111111
Typ Byte x1000000
Max Byte x0000000
Sub-Address03, Pin 15,= 50kHz, Keystone Typ 1.1
VPP
VPP
VPP
HDFKeyst Horizontal Dynamic Focus Keystone
Min A/B Byte xxx11111
Typ Byte xxx10000
Max A/B Byte xxx00000
Sub-Address04,= 50kHz, TypAmp
B/A
A/B
A/B
VERTICAL DYNAMIC FOCUS FUNCTION (positiveparabola)
AMPVDF Vertical Dynamic Focus Parabola (added horizontal one) Amplitude with VOUT
and VPOS Typical
Min. Byte 000000
Typ. Byte 100000
Max. Byte 111111
Sub-Address0F
VPP
VPP
VPP
VDFAMP Parabola Amplitude Functionof VAMP
(tracking between VAMP and VDF) with
VPOS Typ.
(see Figure1 and Note3)
Sub-Address05
Byte 10000000
Byte 11000000
Byte 11111111
VPP
VPP
VPP
VHDFKeyt Parabola Assymetry Functionof VPOS
Control (tracking between VPOS and VDF)
with VAMP Max.
Sub-Address06
Byte x0000000
Byte x1111111
Notes:1. DutyCycleis theratioof power transistorOFF time period. Power transistoris OFF when output transistoris OFF. Initial Conditionfor Safe Operation StartUpS andC correctionare inhibitedso theoutput sawtoothhas alinearshape.
TDA91107/29
VERTICAL SECTION
Operating Conditions
Symbol Parameter Test Conditions Min. Typ. Max. UnitOUTPUTS SECTION
VEWM Maximum EW OutputVoltage Pin24 6.5 V
VEWm Minimum EW Output Voltage Pin24 1.8 V
RLOAD Minimum Loadfor less than 1% Vertical Amplitude Drift Pin20 65 MΩ
Electrical Characteristics(VCC= 12V,Tamb =25oC)
Symbol Parameter Test Conditions Min. Typ. Max. UnitVERTICAL RAMP SECTION
VRB Voltageat Ramp Bottom Point VREF-V=8V, Pin22 2 V
VRT Voltageat Ramp Top Point (with Synchro)VREF-V Pin22 5 V
VRTF Voltageat Ramp Top Point (without Synchro) Pin22 VRT-
VSTD Vertical Sawtooth Discharge Time Duration (Pin
22)
With 150nF Cap 70 μs
VFRF Vertical Free Running Frequency
(see Notes4&5)
COSC(Pin22)= 150nF
Measuredon Pin22
100 Hz
ASFR AUTO-SYNC Frequency C22= 150nF ±5%
See Note6 165 Hz
RAFD Ramp Amplitude Drift versus Frequencyat
Maximum Vertical Amplitude
C22= 150nF
50Hz
200 ppm/Hz
Rlin Ramp Linearityon Pin22 (see Notes4&5) 2.5Vpos Vertical Position Adjustment Voltage
(Pin23- VOUT centering)
Sub Address06
Byte x0000000
Byte x1000000
Byte x1111111 3.65
3.3 V
VOR Vertical Output Voltage
(peak-to-peakon Pin 23)
Sub Address05
Byte x0000000
Byte x1000000
Byte x1111111 3.5
2.5 V
VOI Vertical Output Maximum Current (Pin23) ±5mA
dVS Max Vertical S-Correction Amplitude
x0xxxxxx inhibits S-CORR
x1111111 gives max S-CORR
Subaddress07
ΔV/VPPat T/4
ΔV/VPPat 3T/4
Ccorr Vertical C-Corr Amplitude
x0xxxxxx inhibits C-CORR
SubAddress08
Byte x1000000
Byte x1100000
Byte x1111111
Notes:4. With Register07at Bytex0xxxxxx (VerticalS-Correction Control) thentheS correctionis inhibited, consequentlythe sawtoothhas linearshape. With Register08at Byte x0xxxxxx (VerticalC- Correction Control)thentheC correctionis inhibited, consequentlythe sawtooth
hasa linearshape.It isthe frequency rangefor whichthe VERTICAL OSCILLATORwill automaticallysynchronize, usinga single capacitor valueon
Pin22and with aconstantramp amplitude.
TDA9110
8/29
VERTICAL SECTION (continued)
Electrical Characteristics(VCC= 12V,Tamb =25oC) (continued)
Symbol Parameter Test Conditions Min. Typ. Max. Unit
EAST/WEST FUNCTION
EWDC DC Output Voltage with Typ Vpos,Keystone,
Corner and Corner Balance Inhibited
Pin24, see Figure2 2.5 V
TDEWDC DC OutputVoltage Thermal Drift See Note7 100 ppm/C
EWpara Parabola Amplitude with Vamp Max,
V-Pos Typ, Keystone Inhibited
Subaddress0A
Byte 11111111
Byte 10100000
Byte 10000000
EWtrack Parabola Amplitude Functionof V-AMP Control
(tracking between V-AMP and E/W) with Typ
Vpos, Keystone, EW Typ Amplitude
(see Note8)
Subaddress05
Byte 10000000
Byte 11000000
Byte 11111111
KeyAdj Keystone Adjustment Capability with TypVpos, Inhibited and Vertical Amplitude Max.
(see Note8 and Figure4)
Subaddress09
Byte 1x000000
Byte 1x111111
VPP
VPP
KeyTrack Intrinsic Keystone Functionof V-POS Control
(tracking between V-POS and EW) with EW
Max Amplitude and Vertical Amplitude Max.
(see Note8)
A/B Ratio
B/A Ratio
Subaddress06
Byte x0000000
Byte x1111111
0.52 HSIZE OUTPUT CONTROL
HSize out DC HSize Output Level (Pin28) Subaddress0B
Byte 00000000
Byte 01000000
Byte 01111111
INTERNAL HORIZONTAL DYNAMIC PHASE CONTROL FUNCTION
SPBpara SidePinBalance ParabolaAmplitude (Figure3)
with Vamp Max, V-POS Typ and Parallelogram
Inhibited (see Notes8&9)
Subaddress0D
Byte x1111111
Byte x1000000
+1.4
%TH
%TH
SPBtrack Side Pin Balance Parabola Amplitude function Vamp Control (tracking between Vamp and
SPB) with SPB Max, V-POS Typ and
Parallelogram Inhibited (see Notes8&9)
Subaddress05
Byte 10000000
Byte 11000000
Byte 11111111
%TH
%TH
%TH
ParAdj ParallelogramAdjustment Capability with Vamp
Max, V-POS Typ and SPB Max
(see Notes8&9)
Subaddress0E
Byte x1111111
Byte x1000000
+1.4
%TH
%TH
Partrack Intrinsic ParallelogramFunctionof VposControl
(trackingbetweenV-Pos andDHPC) with Vamp
Max, SPB Max and Parallelogram Inhibited
(see Notes8&9)
A/B Ratio
B/A Ratio
Subaddress06
Byte x0000000
Byte x1111111
VERTICAL MOIRE
VMOIRE Vertical Moire (measuredon VOUTDC)(Pin23) Subaddress0C
Byte 01x11111 6 mV
BREATHING COMPENSATION
BRADj Vertical Output Variation versus DC Breathing
Control (Pin 23)
V18 >VREF-V
V18 =VREF-V
V18 =VREF-V -4V
Notes:7. These parametersarenot testedon each unit.Theyare measured duringour internalqualification Refersto Notes4&5 fromlast section.THisthe Horizontal PLL PeriodDuration.
TDA9110
9/29
VDFDCVDFAMP
3.E
Figure1: Vertical Dynamic Focus Function
DHPCDC
SPBPARA
Figure3: Dynamic Horizontal Phase Control
Output
EWDC
EWPARA
4.E
Figure2: E/W Output
Keyadj
Figure4: KeystoneEffecton E/W Output
(PCC Inhibited)
TDA9110
10/29
TYPICALVERTICAL OUTPUT WAVEFORMS
Function Sub
Address Pin Byte Specification Picture Image
Vertical Size 05 23
Vertical
Position
Control 23
x0000000
x1000000
x1111111
3.2V
3.5V
3.8V
Vertical
Linearity 23
0xxxxxxx
Inhibited
1x111111
Vertical
Linearity 23
1x000000
1x111111
3.E
2.25V
3.75VVOUTDC
VOUTDC
VPP
VPP =4%
VPP
VPP =3%VPP
VPP =3%
TDA9110
11/29
GEOMETRY OUTPUT WAVEFORMS
Function Sub
Address Pin Byte Specification Picture Image
Trapezoid
Control 09 24
EWamp
Inhibited.
1X000000
1X111111
Pin Cushion
Control 0A 24
Keystone
Inhibited
Parrallelogram
Control 0E Internal
SPB
Inhibited
1x000000
1x111111
Side Pin
Balance
Control Internal
Parallelogram
Inhibited
1x000000
1x111111
Vertical
Dynamic
Focus
with Horizontal
2.5V
2.5V
0.9V
0.9V
2.5V
2.5V
1.4%TH3.7V
3.7V 1.4%TH
1.4%TH
3.7V
1.4%TH
3.7V
TDA9110
12/29
2C BUSADDRESS TABLESubAddress Definition
Slave Address (8C): Write Mode D7 D6 D5 D4 D3 D2 D1 x x x x 0 0 0 0 Horizontal Drive Selection/ Horizontal Duty Cycle x x x x 0 0 0 1 Horizontal Position x x x x 0 0 1 0 Horizontal Moiré Control x x x x 0 0 1 1 Synchro Priority/ Horizontal Focus Amplitude x x x x 0 1 0 0 Refresh/ Horizontal Focus Keystone x x x x 0 1 0 1 Vertical Ramp Amplitude x x x x 0 1 1 0 Vertical Position Adjustment x x x x 0 1 1 1 S Correction x x x x 1 0 0 0 C Correction x x x x 1 0 0 1 E/W Keystone x x x x 1 0 1 0 E/W Amplitude x x x x 1 0 1 1 Horizontal Size Control x x x x 1 1 0 0 Vertical Moiré x x x x 1 1 0 1 Side Pin Balance x x x x 1 1 1 0 Parallelogram x x x x 1 1 1 1 Vertical Dynamic Focus Amplitude
Slave Address (8D): ReadMode D7 D6 D5 D4 D3 D2 D1 x x x x 0 0 0 0 Synchro and Polarity Detection
TDA9110
13/29
D7 D6 D5 D4 D3 D2 D1WRITE MODE
HDriveoff
[1],on
Horizontal Duty Cycle
[0] [0] [0] [0] [0]
Xray reset
[0]
Horizontal Phase Adjustment
[1] [0] [0] [0] [0] [0] [0]
HMoire
1,on
[0],off
Horizontal Moire Amplitude
[0] [0] [0] [0] [0]
Sync Comp
[1], Sep
Horizontal Focus Amplitude
[1] [0] [0] [0] [0] [0] [0]
Detect
Refresh
[0],off
Horizontal Focus Keystone
[1] [0] [0] [0] [0]
Vramp
0,off
[1],on
Vertical Ramp Amplitude Adjustment
[1] [0] [0] [0] [0] [0] [0] Vertical Position Adjustment
[1] [0] [0] [0] [0] [0] [0] Select
1,on
[0] Correction
[1] [0] [0] [0] [0] [0] Select
1,on
[0] Correction
[1] [0] [0] [0] [0] [0] Key
0,off
[1]
East/West Keystone
[1] [0] [0] [0] [0] [0]Sel
0,off
[1]
East/West Amplitude
[1] [0] [0] [0] [0] [0] [0]
TestH
1,on
[0],off
HSize Control
[1] [0] [0] [0] [0] [0] [0]
TestV
1,on
[0],off
Moireon
[0]
Vertical Moire
[0] [0] [0] [0] [0]
SPB Sel
0,off
[1]
Side Pin Balance
[1] [0] [0] [0] [0] [0]
Parallelo
0,off
[1]
Parallelogram
[1] [0] [0] [0] [0] [0] Vertical Dynamic Focus Amplitude
[1] [0] [0] [0] [0] [0]
READ MODE
Hlock
0,on
[1],no
Vlockon
[1],no
Xrayon
[0],off
Polarity Detection Synchro Detection
H/Vpol
[1], negativepol
[1], negative
Vextdet
[0],nodet
H/V det
[0],nodet det
[0],nodet initial value
Data are transferred with vertical sawtooth retrace.2C BUSADDRESS TABLE (continued)
TDA9110
14/29
OPERATING DESCRIPTION- GENERAL CONSIDERATIONS
I.1- Power Supply
The typical valuesof the power supply voltages
VCC and VDD are 12V and 5V respectively. Perfect
operationis obtained for VCC between 10.8 and
13.2V and VDD between 4.5 and 5.5V. orderto avoid erratic operationof the circuit
during transient phaseof VCC switching on,or off,
the valueof VCCis monitored and the outputsof
the circuit are inhibitedif VCCis less than 7.5V
typically.
Similarly,VDDis monitored and internally set-up
until VDD reaches 4V (seeI2C Control Table for
poweron reset).
Inordertohavea verygoodpowersupply rejection,
the circuitis internally suppliedby several voltage
references(typical value: 8V).Twoof thesevoltage
references are externally accessible, one for the
vertical and one for the horizontal part.If needed,
these voltage references can be used(if ILOADis
less than 5mA).Itis necessaryto filter the a.m.
voltage references by external capacitors con-
nectedto ground,in orderto minimize the noise
and consequently the ”jitter”on vertical and hori-
zontal output signals.
I.2-I2C Control
TDA9110belongsto theI2C controlleddevice fam-
ily. Insteadof being controlledby DC voltageson
dedicated control pins, each adjustment can be
done via theI2C Interface.
TheI2C busisa serial bus witha clock anda data
input.Thegeneral functionandthebus protocolare
specifiedin the Philips-bus data sheets.
The interface (Data and Clock)is TTL-level com-
patible. The internal threshold levelof the input
comparatoris 2.2V (when VDDis 5V). Spikes (up 50ns) are filteredbyan integratorand the clock
speedis limitedto 400kHz.
Thedataline (SDA) canbe used bidirectionally(i.e. read-mode theIC clocks outa reply information byte)to the micro-processor).
The bus protocol prescribes alwaysa full-byte
transmission. The first byte after thestart condition usedto transmit the IC-address(7 bits-8C) and
the read/writebit(0 write-1 read).
I.3- Write Mode write mode the second byte sent contains the
subaddressof the selected functionto adjust (or
controlsto affect)andthe thirdbytethe correspond-
ing data byte.Itis possibleto send more than one
data byteto the IC.If after the third byteno stopor
start conditionis detected, the circuit increments
automaticallyby onethemomentarysubaddressin
the subaddress counter (auto-increment mode).itis possibleto transmit immediately the next
data bytes without sending the IC address or
subaddress.It can beusefultoreinitializethe whole
controls very quickly (flash manner). This proce-
dure canbe finishedbya stop condition.
The circuit has16 adjustmentcapabilities: 2forthe
Horizontal part,4 for the Vertical,2 for the E/W
correction,2 for the Dynamic Horizontal phase
control,2for the Moire options,3for the Horizontal
and Vertical Dynamic Focus and1 for the HSize
amplitude control. bits are also dedicatedto several controls
(ON/OFF, Synchro Priority, Detection Refresh and
Xray reset).
I.4- Read Mode
During the read mode the second byte transmits
the reply information.
The reply bytecontains the Horizontal and Vertical
Lock/Unlockstatus, the Xray activation status and,
the Horizontaland Verticalpolaritydetection.It also
contains the Synchro detection status whichis
usedby the MCUto assign the Synchro priority.
Astopconditionalwaysstops allthe activitiesof the
bus decoderand switchesto high impedanceboth
for the data and the clock line (SDA and SCL).
SeeI2C Subaddressand control tables.
I.5- Synchro Processor
TheinternalSynchroProcessor allowsthe TDA9110 acceptany kindof input synchro signals: separated Horizontal& Vertical TTL-compatible
synchro signals, composite Horizontal &Vertical TTL-compatible
synchro signals.
I.6- Synchro Identification Status
The MCU can choose via theI2C the synchro
priority thanksto the system identification status
providedby the TDA9110. The extracted Vertical
synchro pulseis available when this identification
status has been received and when the 12Vis
supplied. Evenin Powermanagementmode theIC ableto informthe MCUthat synchrosignalswere
detected duetoits 5V supply. We recommendto
use the deviceas following: first, refresh the syn-
chro detectionbyI2C, then check the statusof H/V
det and VdetbyI2C read.
Sync priority choice shouldbe:
Vext
det
H/V
det
det
Sync priority
Subaddress03 Comment D7 Synchro type Yes Yes 1 1 SeparatedH&V
Yes Yes No 0 1 Composite TTL
H&V
TDA9110
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