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TDA9109/SN
LOW-COST DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
TDA9109/SNLOW-COST DEFLECTION PROCESSOR
FOR MULTISYNC MONITORS
June 1998
PRELIMINARY DATA
SHRINK32(Plastic Package)
ORDER CODE: TDA9109/SN
HORIZONTAL. SELF-ADAPTATIVE. DUAL PLL CONCEPT. 150kHz MAXIMUM FREQUENCY. X-RAYPROTECTION INPUT.I2C CONTROLS: H-POSITION, FREQUENCY
GENERA TORFOR BURN-IN MODE
VERTICAL. VERTICAL RAMP GENERATOR.50 TO 185Hz AGC LOOP. GEOMETRYTRACKING WITH VPOS& VAMP.I2C CONTROLS:
VAMP, VPOS, S-CORR, C-CORR. DC BREATHINGCOMPENSATION
2
C GEOMETRYCORRECTIONS. VERTICAL PARABOLA GENERATOR
(Pin Cushion- E/W, Keystone,Corner). HORIZONTAL DYNAMIC PHASE
(Side Pin Balance& Parallelogram). VERTICAL DYNAMIC FOCUS
(Vertical Focus Amplitude)
GENERAL. SYNC PROCESSOR. 12V SUPPLY VOLTAGE.8V REFERENCE VOLTAGE. HOR.& VERT. LOCK/UNLOCK OUTPUTS. READ/WRITEI2C INTERFACE. HORIZONTAL AND VERTICAL MOIRE.B+ REGULATOR INTERNAL PWM GENERATOR FOR B+
CURRENT MODE STEP-UPCONVERTER SOFTSTART2C ADJUSTABLEB+REFERENCEVOLTAGE OUTPUT PULSES SYNCHRONIZED ON
HORIZONTAL FREQUENCY INTERNALMAXIMUMCURRENT LIMITATION. COMPARED WITH THE TDA9109,
THE TDA9109/SNHAS: CORNER CORRECTION, HORIZONTAL MOIRÉ, B+ SOFT START, INCREASED MAX.VERTICALFREQUENCY, NO HORIZONTAL FOCUS, NOSTEPDOWNOPTIONFOR DC/DC CON-
VERTER,
-NOI2C FREE RUNNING ADJUSTMENT, FIXED HORIZONTAL DUTY CYCLE (48%), INCREASED MAXIMUM STORAGE TIME THE HORIZONTAL SCANNING TRAN-
SISTOR.
DESCRIPTIONThe TDA9109/SNisa monolithic integrated circuit
assembledin 32-pinshrinkdualin line plasticpack-
age. ThisIC controlsall the functionsrelatedto the
horizontal and vertical deflectionin multimodeor
multi-frequencycomputer display monitors.
Theinternalsyncprocessor, combinedwith thevery
powerful geometry correction block make the
TDA9109/SN suitable for very high performance
monitors, using very few externalcomponents.
Thehorizontaljitter level isverylow. Itisparticularly
well suitedfor high-end 15” and 17” monitors.
Combined with the ST7275 Microcontroller fam-
ily, TDA9206 (Video preamplifier) and STV942x
(On-Screen Display controller) the TDA9109/SN
allows fullyI2C bus controlled computer display
monitorsto be built witha reduced numberof
external components.
1/30
SDA
SCL
VCC
GND
HOUT
XRAY
EWOUT
VOUT
VCAP
VREF
VAGCCAP
VGND
BREATH
B+GNDISENSE
REGIN
COMP
HREF
HFLY
HGND
FOCUS-OUT
HMOIRE
HPOSITION
PLL1F
PLL2C
HLOCKOUT
H/HVIN
VSYNCIN
BOUT
PIN CONNECTIONS
TDA9109/SN
2/30
PIN CONNECTIONS
Pin Name Function H/HVIN TTL compatible Horizontal sync Input (separateor composite) VSYNCIN TTL compatible Vertical sync Input (for separated H&V) HLOCKOUT First PLL Lock/Unlock Output (0V unlocked-5V locked) PLL2C Second PLL LoopFilter C0 Horizontal Oscillator Capacitor R0 Horizontal Oscillator Resistor PLL1F First PLL Loop Filter HPOSITION Horizontal Position Filter (capacitortobe connectedto HGND) HMOIRE Horizontal Moiré Output(tobe connectedto PLL2C througha resistor divider) FOCUSOUT Vertical Dynamic Focus Output HGND Horizontal Section Ground HFLY Horizontal Flyback Input (positive polarity) HREF Horizontal Section Reference Voltage(tobe filtered) COMP B+ Error Amplifier Outputfor frequency compensation and gain setting REGIN Regulation InputofB+ control loop ISENSE Sensing ofexternalB+ switching transistor current B+GND Ground (related toB+ reference adjustment) BREATH DC Breathing Input Control (compensationof vertical amplitude against EHV variation) VGND Vertical Section Ground VAGCCAP Memory Capacitorfor Automatic Gain Control Loopin Vertical Ramp Generator VREF Vertical Section Reference Voltage(tobe filtered) VCAP Vertical Sawtooth Generator Capacitor VOUT Vertical Ramp Output (withfrequency independant amplitude andSorC Correctionsif any).is mixed with vertical position voltage and vertical moiré. EWOUT Pin Cushion- E/W Correction Parabola Output HOUT Horizontal Drive Output (internaltransistor, open collector) XRAY X-RAY protection input (with internal latch function) GND General Ground (referencedto VCC) BOUT B+ PWM Regulator Output VCC Supply Voltage (12V typ) SCL I2C Clock Input SDA I2C Data Input 5V Supply Voltage (5V typ.)
TDA9109/SN
3/30
QUICK REFERENCE DATA
Parameter Value UnitHorizontal Frequency 15to 150 kHz
Autosynch Frequency (for givenR0 and C0) 1to4.5f0 Horizontal Sync Polarity Input YES
Polarity Detection (on bothHorizontal and Vertical Sections) YES
TTL Composite Sync YES
Lock/Unlock Identification(on both Horizontal1st PLL and Vertical Section) YES2C Controlfor H-Position ±10 %
XRAY Protection YES2C Horizontal Duty Fixed 48 %2C Free Running Frequency Adjustment NO
Stand-by Function YES
Dual Polarity H-Drive Outputs NO
Supply Voltage Monitoring YES
PLL1 Inhibition Possibility NO
Blanking Outputs NO
Vertical Frequency 35to 200 Hz
Vertical Autosync (for 150nFon Pin22 and 470nFon Pin20) 50to 185 Hz
Vertical S-Correction YES
Vertical C-Correction YES
Vertical Amplitude Adjustment YES Breathing Controlon Vertical Amplitude YES
Vertical Position Adjustment YES
East/West (E/W) Parabola Output (also knownas Pin Cushion Output) YES
E/W Correction Amplitude Adjustment YES
Keystone Adjustment YES
Corner Correction YES
Internal Dynamic Horizontal Phase Control YES
Side Pin Balance Amplitude Adjustment YES
Parallelogram Adjustment YES
Trackingof Geometric Corrections with Vertical Amplitude and Position YES
Reference Voltage (bothon Horizontal and Vertical) YES
Vertical Dynamic Focus YES2C Horizontal Dynamic Focus Amplitude Adjustment NO2C Horizontal Dynamic Focus Symmetry Adjustment NO2C Vertical Dynamic Focus Amplitude Adjustment YES
Detectionof InputSync Type YES
Vertical Moiré Output YES
Horizontal Moiré Output YES2C Controlled Moiré Amplitude YES
Frequency Generatorfor Burn-in YES
FastI2C Read/Write 400 kHz Regulation adjustablebyI2C YES Soft Start YES
TDA9109/SN
4/30
REF
HSY
HORIZONTAL
MOIRE
CANCEL
BITS+ON/OFF
HMOIRE
HREF
HGND
SYNC
PROCESSOR
SYNC
INPUT
SELECT
bit)
CONTROLLER
LOCK/UNLOCK
IDENTIFICATION
PHASE
COMPARATOR
PHASE
SHIFTER
H-DUTY
(48%)
HOUT
BUFFER
VCO
Forced
Frequency
bits
VAMP
bits19 31 27
REF
VGND
SDA SCL
GND
REF
AND
CORRECTION
VERTICAL
OSCILLATOR
RAMP
GENERATOR
GEOMETRY
TRACKING
bits
bits
Keyst.
bits
E/W
bits
PLL1F
HLOCKOUT
HPOSITION
HFLY
PLL2C
HOUT
VCAP
VAGCCAP
VOUT
VSYNCIN
H/HVIN
EWOUT29
XRAY
RESET
GENERATOR
INTERFACE
VPOS
bits
AMPVDF
bits
FOCUS
Parallelogram
bits
Spin
Bal
bits
VSYNC
SAFETY
PROCESSOR
XRAYV
BGND
SENSE
REGIN
B+OUT
COMP
Adjust
bits BREATH
PHASE/FREQUENCY
COMPARATOR
H-PHASE
bits)
VERTICAL
MOIRE
CANCEL
BITS+ON/OFF
Corner
bits
TDA9109/SN2.E
BLOCK DIAGRAM
TDA9109/SN5/30
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value UnitVCC Supply Voltage (Pin 29) 13.5 V
VDD Supply Voltage (Pin 32) 5.7 V
VIN Max Voltageon Pin4
Pin5
Pins6,7,8,14,15, 16,20,22
Pins9,10, 18,23,24,25, 26,28
Pins1,2,3,30,31
VCC
VDD
VESD ESD susceptibility Human Body Model,100pF Discharge through 1.5kΩ
EIAJ Norm, 200pF Discharge through0Ω
Tstg Storage Temperature -40, +150 oC Junction Temperature +150 oC
Toper Operating Temperature 0, +70 oC
09S
THERMAL DATA
Symbol Parameter Value UnitRth(j-a) Junction-Ambient Thermal Resistance Max. 65 o C/W
4.T
SYNC PROCESSOR
Operating Conditions (VDD =5V,Tamb =25oC)
Symbol Parameter Test Conditions Min. Typ. Max. UnitHsVR Voltageon H/HVIN Input Pin1 0 5 V
MinD Minimum Horizontal Input Pulses Duration Pin1 0.7 μs
Mduty Maximum Horizontal Input Signal Duty Cycle Pin1 25 %
VsVR Voltageon VSYNCIN Pin2 0 5 V
VSW Minimum Vertical Sync Pulse Width Pin2 5 μs
VSmD Maximum Vertical SyncInput Duty Cycle Pin2 15 %
VextM Maximum VerticalSync Widthon TTL H/Vcomposite Pin1 750 μs
IHLOCKOUT Sink and SourceCurrent Pin3 250 μA
Electrical Characteristics(VDD =5V, Tamb =25oC)
Symbol Parameter Test Conditions Min. Typ. Max. UnitVINTH Horizontal and Vertical Input Logic Level
(Pins1,2)
Low Level
High Level 2.2
0.8 V
RIN Horizontal and Vertical Pull-Up Resistor Pins1,2 200 kΩ
TfrOut Fall and Rise Time, Output CMOS Buffer Pin3, COUT= 20pF 200 ns
VHlock Horizontal1st PLL Lock Output Status (Pin3) Locked, ILOCKOUT= -250μA
Unlocked, ILOCKOUT= +250μA 4.4
0.5 V
VoutT Extracted Vsync Integration Time(%of TH) H/V Composite (see Note1)= 820pF 26 35 %
Note1:THisthe horizontal period.
2
C READ/WRITE (see Note2)
Electrical Characteristics (VDD =5V,Tamb =25oC)
Symbol Parameter Test Conditions Min. Typ. Max. Unit2C PROCESSOR
Fscl Maximum Clock Frequency Pin30 400 kHz
Tlow Low periodof the SCL Clock Pin30 1.3 μs
Thigh High periodofthe SCL Clock Pin30 0.6 μs
Vinth SDA and SCL Input Threshold Pins 30,31 2.2 V
VACK Acknowledge Output Voltageon SDA input with 3mA Pin31 0.4 V
Note2: See alsoI2C Table ControlandI2C Sub Address Control.
TDA9109/SN
6/30
HORIZONTAL SECTION
Operating Conditions
Symbol Parameter Test Conditions Min. Typ. Max. UnitVCO
R0(Min.) Minimum Oscillator Resistor Pin6 6 kΩ
C0(Min.) Minimum Oscillator Capacitor Pin5 390 pF
F(Max.) Maximum Oscillator Frequency 150 kHz
OUTPUT SECTION
I12m Maximum Input Peak Current Pin12 5 mA
HOI Horizontal Drive Output Maximum Current Pin26, Sunk current 30 mA
Electrical Characteristics(VCC= 12V,Tamb =25oC)
Symbol Parameter Test Conditions Min. Typ. Max. UnitSUPPLY AND REFERENCE VOLTAGES
VCC Supply Voltage Pin29 10.8 12 13.2 V
VDD Supply Voltage Pin32 4.5 5 5.5 V
ICC Supply Current Pin29 50 mA
IDD Supply Current Pin32 5 mA
VREF-H Horizontal Reference Voltage Pin13,I= -2mA 7.4 8 8.6 V
VREF-V Vertical Reference Voltage Pin21,I= -2mA 7.4 8 8.6 V
IREF-H Max. Sourced Currenton VREF-H Pin13 5 mA
IREF-V Max. Sourced Currenton VREF-V Pin21 5 mA
1st PLL SECTION
HpolT Delay Timefor detecting polarity change
(see Note3)
Pin1 0.75 ms
VVCO VCO Control Voltage (Pin7) VREF-H =8V f0
fH(Max.)
Vcog VCO Gain (Pin7) R0= 6.49kΩ,C0= 820pF,
dF/dV= 1/11R0C0
17.1 kHz/V
Hph Horizontal Phase Adjustment (see Note4) %of Horizontal Period ±10 %
Vbmin
Vbtyp
Vbmax
Horizontal Phase SettingValue (Pin 8)(see Note4)
Minimum Value
TypicalValue
Maximum Value
Sub-Address01
Byte x1111111
Byte x1000000
Byte x0000000
IPll1U
IPll1L
PLL1 Filter Current Charge PLL1is Unlocked
PLL1is Locked ±140±1 μA Free RunningFrequency R0= 6.49kΩ,C0= 820pF,= 0.97/8R0C0
22.8 kHz
df0/dT Free RunningFrequency Thermal Drift
(No drifton external components) (see Note5)
-150 ppm/C PLL1 CaptureRange R0= 6.49kΩ,C0= 820pF,
from f0+0.5kHzto 4.5f0
fH(Min.)
fH(Max.) 90 kHz
kHz Forced Frequency FF1 Byte 11xxxxxx
FF2 Byte 10xxxxxx
Sub-Address02 2f0
3f0
Notes:3. This delayis mandatoryto avoida wrongdetectionof polarity changeinthe caseofa composite sync. See Figure10for explanationof reference phase. These parametersarenot testedon each unit.Theyare measured duringour internalqualification. This PLLcapturerange maybe obtained onlyiff0is captured(for instancebu adjustingR0).If not, moremargin mustbe provided
betweenfH (Min.)andf0,to cope withthe componentsspread.
5.T
TDA9109/SN7/30
HORIZONTAL SECTION (continued)
Electrical Characteristics(VCC= 12V,Tamb =25oC) (continued)
Symbol Parameter Test Conditions Min. Typ. Max. Unit2nd PLL SECTION AND HORIZONTAL OUTPUT SECTION
FBth Flyback Input Threshold Voltage (Pin 12) 0.65 0.75 V
Hjit Horizontal Jitter At 31.4kHz 70 ppm Horizontal Drive Output Duty-Cycle
(Pin26) (see Note7) %
XRAYth X-RAYProtection Input ThresholdVoltage Pin25, see Note8 8 V
Vphi2 Internal Clamping Levelson 2nd PLL
Loop Filter (Pin4)
Low Level
High Level
VSCinh Threshold Voltageto Stop H-Out,V-Out,
B-Out and Reset XRAY
when VCC< VSCinh (see Note8)
Pin29 7.5 V
VSDinh Threshold Voltageto Stop H-Out,V-Out,
B-Out and Reset XRAY
when VDD< VSDinh
Pin32 4.0 V
HDvd Horizontal Drive Output (low level) Pin26, IOUT= 30mA 0.4 V
VERTICAL DYNAMIC FOCUS FUNCTION (positive parabola)
HDFDC Bottom DC Output Level RLOAD= 10kΩ, Pin10 2 V
TDHDF DC Output Voltage Thermal Drift (see
Note5)
200 ppm/C
AMPVDF Vertical Dynamic Focus Parabola
Amplitude with VAMP and VPOS Typical
Min. Byte 000000
Typ. Byte 100000
Max. Byte 111111
Sub-Address0F
VPP
VPP
VPP
VDFAMP Parabola Amplitude Functionof VAMP
(tracking between VAMP and VDF) with
VPOS Typ. (see Figure1 and Note9)
Sub-Address05
Byte 10000000
Byte 11000000
Byte 11111111
VPP
VPP
VPP
VHDFKeyt Parabola Asymetry Functionof VPOS
Control (trackingbetween VPOS andVDF)
with VAMP Max.
Sub-Address06
Byte x0000000
Byte x1111111
VPP
VPP
Notes:5. These parametersarenot testedon each unit.Theyare measured duringour internalqualification. Duty Cycleisthe ratio betweenthe output transistor OFF timeandthe period.The power transistoris controlledOFF whenthe
output transistoris OFF. Initial Conditionfor Safe Operation StartUp See Figure14.S andC correctionare inhibitedso theoutput sawtoothhas alinearshape.
TDA9109/SN8/30
VERTICAL SECTION
Operating Conditions
Symbol Parameter Test Conditions Min. Typ. Max. UnitOUTPUTS SECTION
VEWM Maximum E/W OutputVoltage Pin24 6.5 V
VEWm Minimum E/W Output Voltage Pin24 1.8 V
RLOAD Minimum Loadfor less than 1% VerticalAmplitude Drift Pin20 65 MΩ
Electrical Characteristics(VCC= 12V,Tamb =25oC)
Symbol Parameter Test Conditions Min. Typ. Max. UnitVERTICAL RAMP SECTION
VRB Voltageat Ramp Bottom Point VREF-V= 8V,Pin22 2 V
VRT Voltageat Ramp Top Point (with Sync) VREF-V= 8V,Pin22 5 V
VRTF Voltageat Ramp Top Point (without Sync) Pin22 VRT-0.1 V
VSTD Vertical Sawtooth Discharge Time Pin22, C22= 150nF 70 μs
VFRF Vertical Free Running Frequency
(see Note10)
COSC(Pin22)= 150nF
Measuredon Pin22
100 Hz
ASFR AUTO-SYNC Frequency (see Note 11) C22= 150nF ±5% 50 185 Hz
RAFD Ramp Amplitude Drift Versus Frequencyat
Maximum Vertical Amplitude (see Note5)
C22= 150nF
50Hz
200 ppm/Hz
Rlin Ramp Linearityon Pin22 (see Note10) 2.5V< V27 and V27< 4.5V 0.5 %
VPOS Vertical Position Adjustment Voltage
(Pin23- VOUT mean value)
Sub Address06
Byte x0000000
Byte x1000000
Byte x1111111 3.65
3.3 V
VOR Vertical Output Voltage
(peak-to-peakon Pin 23)
Sub Address05
Byte x0000000
Byte x1000000
Byte x1111111 3.5
2.5 V
VOI Vertical Output Maximum Current (Pin 23) ±5mA
dVS Max Vertical S-Correction Amplitude
(see Note12)
x0xxxxxx inhibits S-CORR
x1111111 givesmax S-CORR
Sub Address07
ΔV/VPPat TV/4ΔV/VPPat 3TV/4
Ccorr Vertical C-Corr Amplitude
x0xxxxxx inhibitsC-CORR
Sub Address08
ΔV/VPP@ TV/2
Byte x1000000
Byte x1100000
Byte x1111111
Notes:5. These parametersare nottestedon each unit. Theyare measured duringour internal qualification.
10. With Register07at Bytex0xxxxxx(S correctionis inhibited)and withRegister08at Bytex0xxxxxx(C correctionis inhibited),the
sawtoothhasa linear shape.
11. Thisisthe frequencyrangefor whichthevertical oscillatorwill automaticallysynchronize,usinga singlecapacitor valueon Pin22
and witha constant ramp amplitude.
12.TVisthe vertical period.
09S
5.T
TDA9109/SN
9/30
VERTICAL SECTION (continued)
Electrical Characteristics(VCC= 12V,Tamb =25oC) (continued)
Symbol Parameter Test Conditions Min. Typ. Max. Unit
East/West (E/W) FUNCTION
EWDC DC Output Voltage with Typ. VPOS,Keystone and
Corner inhibited
Pin24, see Figure2 2.5 V
TDEWDC DC Output Voltage Thermal Drift See Note13 100 ppm/C
EWpara Parabola Amplitude with Max. VAMP, Typ. VPOS,
Keystone and Corner inhibited
Subaddress0A
Byte 11111111
Byte 11000000
Byte 10000000
VPP
VPP
VPP
EWtrack Parabola Amplitude Functionof VAMP Control
(tracking between VAMP and E/W) with Typ.VPOS,
Typ. E/W Amplitude,Keystone and Corner inhibited
(see Note 10)
Subaddress05
Byte 10000000
Byte 11000000
Byte 11111111
VPP
VPP
VPP
KeyAdj Keystone Adjustment Capability with Typ. VPOS,
Corner and E/W inhibited and Max. Vertical
Amplitude (see Note10 and Figure4)
Subaddress09
Byte 1x000000
Byte 1x111111
VPP
VPP
KeyTrack Intrinsic Keystone Functionof VPOS Control
(tracking between VPOS and E/W) with Max. E/W
Amplitude,Max. Vertical Amplitude and Corner
inhibited (see Note13 and Figure2)
A/B Ratio
B/A Ratio
Subaddress06
Byte x0000000
Byte x1111111
Corner Corner Amplitude with Max. VAMP, Typ. VPOS,
Keystone and E/W inhibited
Subaddress0B
Byte 11111111
Byte 11000000
Byte 10000000
VPP
VPP
VPP
INTERNAL DYNAMIC HORIZONTAL PHASE CONTROL
SPBpara SidePinBalanceParabola Amplitude(Figure3) with
Max. VAMP,Typ.VPOSandParallelograminhibited
(see Notes10&14)
Subaddress0D
Byte x1111111
Byte x1000000
+1.4
%TH
%TH
SPBtrack Side Pin Balance Parabola Amplitude functionof
VAMP Control (tracking between VAMP and SPB)
with Max. SPB, Typ. VPOS and Parallelogram
inhibited (see Notes10& 14)
Subaddress05
Byte 10000000
Byte 11000000
Byte 11111111
%TH
%TH
%TH
ParAdj Parallelogram Adjustment Capability with
Max. VAMP, Typ. VPOS and Max. SPB
(see Notes10&14)
Subaddress0E
Byte x1111111
Byte x1000000
+1.4
%TH
%TH
Partrack Intrinsic Parallelogram Functionof VPOS Control
(tracking between VPOS and DHPC) with
Max. VAMP, Max. SPB and Parallelogram inhibited
(see Notes10&14)
A/B Ratio
B/A Ratio
Subaddress06
Byte x0000000
Byte x1111111
VERTICAL MOIRE
VMOIRE Vertical Moiré (measuredon VOUT: Pin23) Subaddress0C
Byte 01x11111 6 mV
BREATHING COMPENSATION
BRRANG DC Breathing Control Range (see Note 15) V18 112 V
BRADj Vertical Output Variation versus DC Breathing
Control (Pin 23)
V18≥ VREF-V
V18 =4V
Notes:10. With Register07at Bytex0xxxxxx(S correctionis inhibited)and withRegister08at Bytex0xxxxxx(C correctionis inhibited),the
sawtoothhasa linear shape.
13. These parametersare nottestedon each unit. Theyare measured duringour internal qualification.
14.TH isthe horizontalperiod.
15. Whennot usedtheDC breathing controlpin mustbe connected to12V.
TDA9109/SN
10/30
SECTIONOperating Conditions
Symbol Parameter Test conditions Min. Typ. Max. Unit
FeedRes Minimum Feedback Resistor Resistor between Pins15 and14 5 kΩ
Electrical Characteristics(VCC= 12V,Tamb =25oC)
Symbol Parameter Test conditions Min. Typ. Max. Unit
OLG Error AmplifierOpen LoopGain At low frequency (see Note 16) 85 dB
ICOMP Sunk Current on Error Amplifier
Output when BOUTisin safety
condition
Pin14 (see Figure14) 0.5 mA
UGBW Unity Gain Bandwidth (see Note 13) 6 MHz
IRI Regulation Input Bias Current Current sourcedby Pin15 (PNP base) 0.2 μA
EAOI Error AmplifierOutput Current Current sourcedby Pin14
Current sunkby Pin14
CSG Current Sense InputVoltage Gain Pin16 3
MCEth Max Current Sense Input Threshold
Voltage
Pin16 1.2 V
ISI Current Sense InputBias Current Current sourcedby Pin16 (PNP base) 1 μA
Tonmax Maximum ON Timeof the external
power transistorof Horizontal period,= 27kHz (see Note 17)
100 %
B+OSV B+ Output Saturation Voltage V28 withI28= 10mA 0.25 V
IVREF Internal Reference Voltage On erroramp (+)inputforSubaddress0B
Byte 1000000
4.8 V
VREFADJ Internal Reference Voltage
Adjustment Range
Byte 1111111
Byte 0000000
+20
tFB+ Fall Time Pin28 100 ns
Notes:13. These parametersare nottestedon each unit. Theyare measured duringour internal qualification.
16. These parametersarenot testedon each unit. Theyare measured duringour internal qualificationprocedure which includes
characterizationon batches coming from cornersofour processes and also temperaturecharacterization.
17. The externalpower transistoris OFFduring about 400ns.
9109S
HDFDCVDFAMP
Figure1: Vertical Dynamic Focus Function
DHPCDC
SPBPARA
9109S
Figure3: Dynamic Horizontal Phase Control
Output
EWDC
EWPARA
Figure2: E/W Output
Keyadj
9109S
Figure4: Keystone Effecton E/W Output
(PCC and Corner Inhibited)
TDA9109/SN
11/30
TYPICALVERTICAL OUTPUT WAVEFORMS
Function Sub
Address Pin Byte Specification Effecton Screen
Vertical Size 05 23
Vertical
Position
Control 23
x0000000
x1000000
x1111111
VOUTDC= 3.2V
VOUTDC= 3.5V
VOUTDC= 3.8V
Vertical
Linearity 23
0xxxxxxx
Inhibited
1x111111
Vertical
Linearity 23
1x000000
1x111111
9109S
9109S
2.25V
3.75VVOUTDC
VOUTDC
VPP
VPP =4%
VPP
VPP =3%VPP
VPP =3%
TDA9109/SN
12/30
GEOMETRY OUTPUT WAVEFORMS
Function Sub
Address Pin Byte Specification Effecton Screen
Keystone
(Trapezoid)
Control 24
E/W+ Corner
inhibited
1x000000
1x111111
E/W
(Pin Cushion)
Control 24
Keystone+
Corner
inhibited
Corner
Control 0B 24
Keystone+
E/W inhibited
Parrallelogram
Control 0E Internal
SPB
inhibited
1x000000
1x111111
Side Pin
Balance
Control Internal
Parallelogram
inhibited
1x000000
1x111111
Vertical
Dynamic
Focus 10
1.7V
2.5V
1.7V
1.4%TH3.7V
3.7V 1.4%TH
1.4%TH
3.7V
1.4%TH
3.7V
2.5V
2.5V
0.65V
0.65V
1.7V
2.5V
TDA9109/SN
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2C BUSADDRESS TABLESlave Address (8C): WriteMode
SubAddress Definition D7 D6 D5 D4 D3 D2 D1 0 0 0 0 0 0 0 0 Horizontal Drive Selection 0 0 0 0 0 0 0 1 Horizontal Position 0 0 0 0 0 0 1 0 Forced Frequency 0 0 0 0 0 0 1 1 Sync Priority/ Horizontal Moiré Amplitude 0 0 0 0 0 1 0 0 Refresh/B+ Reference Adjustment 0 0 0 0 0 1 0 1 Vertical Ramp Amplitude 0 0 0 0 0 1 1 0 Vertical Position Adjustment 0 0 0 0 0 1 1 1 S Correction 0 0 0 0 1 0 0 0 C Correction 0 0 0 0 1 0 0 1 E/W Keystone 0 0 0 0 1 0 1 0 E/W Amplitude 0 0 0 0 1 0 1 1 E/W Corner Adjustment 0 0 0 0 1 1 0 0 Vertical Moiré Amplitude 0 0 0 0 1 1 0 1 Side Pin Balance 0 0 0 0 1 1 1 0 Parallelogram 0 0 0 0 1 1 1 1 Vertical Dynamic Focus Amplitude
Slave Address (8D): Read Mode sub address needed.
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D7 D6 D5 D4 D3 D2 D1WRITE MODE
HDriveoff
[1],on
Xray reset
[0]
Horizontal Phase Adjustment
[1] [0] [0] [0] [0] [0] [0]
Forced Frequency
1,on
[0],off
1,f0x2
[0],f0x3
Sync Comp
[1], Sep
HMoiréon
[0]
Horizontal Moiré Amplitude
[0] [0] [0] [0] [0]
Detect
Refresh
[0],off Reference Adjustment
[1] [0] [0] [0] [0] [0] [0]
Vramp
0,off
[1],on
Vertical Ramp Amplitude Adjustment
[1] [0] [0] [0] [0] [0] [0] Vertical Position Adjustment
[1] [0] [0] [0] [0] [0] [0] Select
1,on
[0] Correction
[1] [0] [0] [0] [0] [0] Select
1,on
[0] Correction
[1] [0] [0] [0] [0] [0]
E/W Key
0,off
[1]
E/W Keystone
[1] [0] [0] [0] [0] [0] E/W Amplitude
[1] [0] [0] [0] [0] [0] [0]
E/W Cor
0,off
[1]
E/W Corner Adjustment
[1] [0] [0] [0] [0] [0] [0]
TestV
1,on
[0],off
VMoiréon
[0]
Vertical Moiré Amplitude
[0] [0] [0] [0] [0]
SPB Sel
0,off
[1]
Side Pin Balance
[1] [0] [0] [0] [0] [0]
Parallelo
0,off
[1]
Parallelogram
[1] [0] [0] [0] [0] [0]
TestH
1,on
[0],off
Vertical Dynamic Focus Amplitude
[1] [0] [0] [0] [0] [0]
READ MODE
Hlock
0,on
[1],no
Vlockon
[1],no
Xrayon
[0],off
Polarity Detection Sync Detection
H/Vpol
[1], negativepol
[1], negative
Vextdet
[0],nodet
H/V det
[0],nodet det
[0],nodet initial value
Datais transferredwith vertical sawtooth retrace. recommendto set the unspecifiedbitto[0]in orderto assure the compatibility with future devices.2C BUSADDRESS TABLE (continued)
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