TDA9105 ,DEFLECTION PROCESSOR FOR MULTISYNC MONITORSTDA9105DEFLECTION PROCESSOR FOR MULTISYNC MONITORSPRELIMINARY DATAHORIZONTAL This IC controls all t ..
TDA9105A ,DEFLECTION PROCESSOR FOR MULTISYNC MONITORSTDA9105ADEFLECTION PROCESSOR FOR MULTISYNC MONITORSPRODUCT PREVIEWHORIZONTAL This IC controls all t ..
TDA9105A ,DEFLECTION PROCESSOR FOR MULTISYNC MONITORSBLOCK DIAGRAM3/3115 12 10 11 8 9 5 3 2 16 4 21 207 19H-REF GNDV-REFPHASE HPHASE PHASE PULSE18VFREQU ..
TDA9106 ,LOW-COST DEFLECTION PROCESSOR FOR MULTISYNC MONITORSTDA9106LOW COST DEFLECTION PROCESSORFOR MULTISYNC MONITORSPRELIMINARY DATAHORIZONTAL Combined with ..
TDA9106A ,LOW COST DEFLECTION PROCESSOR FOR MULTISYNC MONITORSTDA9106ALOW COST DEFLECTION PROCESSORFOR MULTISYNC MONITORSPRELIMINARY DATAHORIZONTALCombined with ..
TDA9106A ,LOW COST DEFLECTION PROCESSOR FOR MULTISYNC MONITORSABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Supply Voltage (Pin 18) 13.5 VCCV Supply Volta ..
TISP6L7591DR , DUAL FORWARD-CONDUCTING P-GATE THYRISTORS PROGRAMMABLE OVERVOLTAGE PROTECTORS
TISP6NTP2C , TISP6NTP2C High Voltage Ringing SLIC Protector
TISP6NTP2CDR , High Voltage Ringing SLIC Protector
TISP7015DR , Three Terminal Very Low Voltage (VLV) Protection
TISP7015DR , Three Terminal Very Low Voltage (VLV) Protection
TISP7038L1DR-S , TRIPLE ELEMENT THYRISTOR OVERVOLTAGE PROTECTORS
TDA9105
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
TDA9105DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
June 1996
PRELIMINARY DATA
SHRINK42(Plastic Package)
ORDER CODE: TDA9105
HORIZONTAL.DUAL PLL CONCEPT.150kHz MAXIMUM FREQUENCY.SELF-ADAPTATIVE.X-RAYPROTECTION INPUT.DC ADJUSTABLE DUTY-CYCLE.1st PLL LOCK /UNLOCK INFORMA TION.WIDE RANGE DC CONTROLLED H-POSI-
TION.ON/OFF SWITCH (FOR PWR MANAGE-
MENT).TWO H-DRIVE POLARITIES.MOIRE OUTPUT
VERTICAL.VERTICAL RAMP GENERATOR.50 TO 165Hz AGC LOOP.DCCONTROLLEDV- AMP,V -POS,S-AMP&C-COR.ON/OFF SWITCH
EWPCC .VERTICAL PARABOLA GENERATOR WITH CONTROLLED KEYSTONE& AMPLITUDE.AUTO TRACKING WITH V-POS& V-AMP
GEOMETRY.WAVE FORM GENERATOR FOR PARALEL-
LOGRAM& SIDE PIN BALANCECONTROL.AUTO TRACKING WITH V-POS& V-AMP
DYNAMIC FOCUS.VERTICAL PARABOLAOUTPUT FOR VERTI-
CAL DYNAMIC FOCUS.AUTO TRACKING WITH V-POS& V-AMP
GENERAL.ACCEPT POSITIVE OR NEGATIVE HORI-
ZONTAL& VERTICAL SYNC POLARITIES.SEPARATEH&V TTL INPUT.COMPOSITE BLANKING OUTPUT
V-FOCUS
H-LOCKOUT
PLL2C
H-DUTY
H-FLY
H-GND
H-REF
FC2
FC1
PLL1F
H-LOCKCAP
PLL1INHIB
H-POS
XRAY-IN
H-SYNC
VCC
GND
H-OUTEM
H-OUTCOL
SPINBAL
KEYBAL
GEOMOUT
EWAMP
KEYST
EWOUT
V-FLY
VDCIN
V-SYNC
V-POS
V-AMP
V-OUT
C-CORR
VS-AMP
V-CAP
V-REF
V-AGCCAP
V-GND
MOIRE
BLK-OUT
VDCOUT
9105-01.EPS
PIN CONNECTIONS
DESCRIPTIONThe TDA9105isa monolithic integrated circuit
assembledina42 pins shrink dualin line plastic
package.
This IC controlsall the functions relatedto the
horizontal and vertical deflectionin multimodesor
multisync monitors.
This IC, combined with TDA9205 (RGB preamp),
STV942x(OSD processor),ST727x (micro control-
ler) and TDA817x (vertical booster), allowsto real-
ize very simple and high quality multimodesor
multisync monitors.
1/32
PIN DESCRIPTION
Pin Name Function V-FOCUS Vertical Dynamic Focus Output H-LOCKOUT First PLL Lock/Unlock Output PLL2C Second PLL Loop Filter H-DUTY DC Controlof HorizontalDrive OutputPulseDuty-cycle.If thisPinisgrounded,the Horizontal
and VerticalOutputsare inhibited.By connectinga Capacitoron thisPina Soft-start function
maybe realizedon H-drive Output. H-FLY Horizontal Flyback Input (positive polarity) H-GND Horizontal Section Ground H-REF Horizontal Section Reference Voltage, mustbe filtered FC2 VCO Low Threshold Filtering Capacitor FC1 VCO High ThresholdFiltering Capacitor C0 Horizontal Oscillator Capacitor R0 Horizontal Oscillator Resistor PLL1F First PLL Loop Filter H-LOCKCAP First PLL Lock/Unlock Time Constant Capacitor. When Frequencyis changing,a Blanking
Pulseis generatedon Pin23,the durationof this Pulseis proportionneltothe Capacitoron
Pin 13. PLL1INHIB TTL-Compatible Inputfor PLL1 Output Current Inhibition H-POS DC Controlfor Horizontal Centering XRAY-IN X-RAY protectionInput (with internal latch function) H-SYNC TTL compatible Horizontal Sync Input VCC Supply Voltage (12V Typ.) GND Ground H-OUTEM Horizontal Drive Output (emiterof internal transistor) H-OUTCOL Horizontal Drive Output (open collectorof internal transistor) BLKOUT Blanking Output, activated during frequency changes, when X-RAYInputis triggered, whenis toolow,or when Device isin stand-by mode(through H-DUTY Pin2)and during H-FLY,
V-FLY, V-SYNC, VSawth retrace. MOIRE Moire Output V-GND Vertical Section Signal Ground V-AGCCAP Memory Capacitorfor Automatic Gain Control Loopin Vertical Ramp Generator V-REF Vertical Section Reference Voltage V-CAP Vertical Sawtooth Generator Capacitor VS-AMP DC Controlof Vertical S-Shape Amplitude C-CORR DC Controlof Vertical C-Correction V-OUT Vertical Ramp Output (with frequency independant amplitude and S-Correction) V-AMP DC Controlof Vertical Amplitude Adjustment VDCOUT Vertical Position Reference Voltage Output V-POS DC Controlof Vertical Position Adjustment V-SYNC TTL-Compatible Vertical Sync Input VDCIN Geometric Correction Reference Voltage Input V-FLY Vertical Flyback Input (positive polarity) EWOUT East /West Pincushion Correction Parabola Output KEYST DC Controlof Keystone Correction EWAMP DC Control East/West Pincushion Correction Amplitude GEOMOUT Side Pin Balance& Parallelogram Correction Parabola Output KEYBAL DC Controlof ParallelogramCorrection SPINBAL DC Control ofSidePin Correction Amplitude
9105-01.TBL
TDA91052/32
PHASE
FREQUENCY
COMP
VCO
PHASE
COMP
-FLY
LL2
PHASE
SHIFTER
LOCK
UNLOCK
IDENT
KOUT
PULSE
SHAPER
-DUTY
RAY
SAFETY
PROCESSOR
OUTPUTBUFFER
H-OUTCO
PULSE
SHAPER
POL
DETECT
H-SYNC
PLL1INHIB
H-REF
H-GND
V-REF
PLL1
INHIB
H-LOCKCAP
CORR
PULSE
SHAPER
POL
DETECT
V-SYNC
V-REF
C-C
V-GND
V-REF
VERT
OSC
RAMP
GENERATOR
VAG
-OUT
V-MID 4241
KEYBAL GEOMOUT SPINBAL 3938
KEYST EWOUT EWAMP
V-FOCUS
BLK
GEN
FLY
-OUT
H-FLY
V-SYNC
MOIRE
GND
TDA9105
VIDEO
UNLOCK
DCIN
DCO
-OUTE
MOIRE
H-Sync V-Sync
9105-02.EPS
BLOCK DIAGRAM
TDA91053/32
QUICK REFERENCE DATA
Parameter Value UnitHorizontal Frequency 15to 150 kHz
Autosynch Frequency (for Given R0, C0) 1to3.7 FH Hor Sync Polarity Input YES
Compatibility with Composite Syncon H-SYNC Input YES (see note1)
Lock/Unlock Identificationon1st PLL YES Controlfor H-Position YES
X-RAY Protection YES
Hor DUTY Adjust YES
Stand-by Function YES
Two Polarities H-Drive Outputs YES
Supply Voltage Monitoring YES
PLL1 Inhibition Input YES
Composite Blanking Output YES
Horizontal Moire Output YES
VerticalFrequency 35to 200 Hz
VerticalAutosync (for 150nF) 50to 165 Hz
VerticalS-Correction YES
VerticalC-Correction YES
VerticalAmplitude Adjustment YES
VerticalPosition Adjustment YES
East/West Parabola Output YES
PCC (Pin Cushion Correction) Amplitude Adjustment YES
Keystone Adjustment YES
Dynamic Horizontal Phase Control Output YES
SidePin Balance Amplitude Adjustment YES
Parallelogram Adjustment YES
Trackingof Geometric Corrections with V-AMP and V-POS YES
Reference Voltage YES (see note2)
Mode Detection NO
VerticalDynamic Focus YES
Notes:1. Provided PLLinhibition inputis used,see application diagramon page27. Onefor Horizontal section andonefor Vertical section.
9105-02.TBL
TDA91054/32
HORIZONTAL SECTION
Operating Conditions
Symbol Parameter Test Conditions Min. Typ. Max. UnitVCO
R0min Oscillator Resistor Min Value (Pin 11) 6 kΩ
C0min Oscillator Capacitor Min Value (Pin 10) 390 pF
Fmax Maximum Oscillator Frequency 150 kHz
HsVR Horizontal Sync Input Voltage (Pin 17) 0 5.5 V
INPUT SECTION
MinD Minimum Input Pulses Duration (Pin 17) 0.7 μS
Mduty Maximum Input Signal Duty Cycle (Pin 17) 25 %
OUTPUT SECTION
I5m Maximum Input Peak Current (Pin5) 5 mA
HOI1
HOI2
Horizontal Drive Output Max Current
Pin20
Pin21
Sourced current
Sink current CONTROL VOLTAGES
DCadj DC Voltageon DC Controls (Pins 4-15) VREF-H =8V 2 6 V
9105-05.TBL
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value UnitVCC Supply Voltage (Pin18) 13.5 V
VIN Max Voltageon Pins4,15, 28,29,31, 33,38,39,41,42
Pin5
Pins 17,34
Pin16
VESD ESD Succeptibility
Human Body Model, 100pFDischarge through 1.5kΩ
EIAJ Norm, 200pF Discharge through0Ω
Tstg Storage Temperature -40, +150 °C Max Operating Junction Temperature 150 °C
Toper Operating Temperature 0, +70 °C
9105-03.TBL
THERMAL DATA
Symbol Parameter Value UnitRth(j-a) Junction-Ambient Thermal Resistance Max. 65 °C/W
9105-04.TBL
TDA91055/32
HORIZONTAL SECTION (continued)
Electrical Characteristics (VCC= 12V, Tamb =25°C)
Symbol Parameter Test Conditions Min. Typ. Max. UnitSUPPLY AND REFERENCE VOLTAGES
VCC Supply Voltage (Pin18) 10.8 12 13.2 V
ICC Supply Current (Pin 18) See Figure1 40 60 mA
VREF-H Reference Voltagefor Horizontal Section (Pin7)I= 2mA 7.4 8 8.6 V
IREF-H Max Sourced Currenton VREF-H (Pin7) 5 mA
VREF-V Reference Voltagefor Vertical Section (Pin26) I= 2mA 7.4 8 8.6 V
IREF-V Max Sourced Currenton VREF-V (Pin 26) 5 mA
INPUT SECTION/PLL1
VINTH Horizontal Input Threshold Voltage (Pin 17) Low level voltage
High level voltage 2
0.8 V
VVCO VCO Control Voltage (Pin 12) VREF-H=8V 1.6to6.2 V
VCOG VCO Gain, dF/dV (Pin 12) R0= 6.49kΩ,C0= 680pF 17 kHz/V
Hph Horizontal Phase Adjust (Pin 15) %of Horizontal period ±12.5 % Free Running Frequency (adjustableby changing R0) R0= 6.49kΩ,C0= 680pF 25 27 29 kHz PLL1 Capture Range Min Max= 6.49kΩ,C0= 680pF
See conditionson Fig.1
3.7xf0
kHz
kHz
PLLinh PLL1 Inhibition (Pin 14) PLL ON
(Typ. Threshold= 1.6V) PLL OFF
V14
V14 2
0.8 V
IHLock0 Max Output Currenton HLock Output I2 10 mA
VHLock0 Low Level Voltageon HLock Output V2 withI2= 10mA 0.25 0.5 V
SECOND PLL AND HORIZONTAL OUTPUT SECTION
FBth Flyback Input Threshold Voltage (Pin5) See Figure14 0.65 0.75 V
Hjit Horizontal Jitter See Application Diagram
(Pins 8-9) ppm
HDmin
HDmax
Horizontal Drive OutputDuty-cycle
(Pin20or 21) (see Note)
Minimum
Maximum =2V =6V =VREF- 100mV
HDvd Horizontal Drive Low Level Output Voltage Pin20to GND,
V21-V20,IOUT= 20mA
1.1 1.7 V
HDem Horizontal Drive High Level Output Voltage
(outputon Pin 20)
Pin21to VCC,
IOUT= 20mA
9.5 10 V
XRAYth X-RAY Protection Input Threshold Voltage (Pin 16) TBD 8 TBD V
ISblkO Maximum Output Currenton Composite
Blanking Output
I22 10 mA
VSblkO Low-Level Voltageon Composite Blanking
Output (Blanking ON)
V22 withI22= 10mA 0.25 0.5 V
ISmoiO Maximum Output Currenton Moire Output I23 10 mA
VSmoiO Low-Level Voltageon Moire Output V23 withI23= 10mA 0.25 0.5 V
Vphi2 Internal Clamping Voltageon 2nd PLL Loop
Filter Output (Pin3)
Vmin
Vmax
VOFF Threshold Voltageto Stop H-out, V-out andto
Activate BLKout (OFF Mode whenV4
(Pin4) 1V
VSCinh Supply Voltageto Stop H-out, V-out when
VCC< VSCinh (Pin18)
TBD 7.5 V
Note: IfH-driveis takenonPin20 (Pin21 connectedto supply),H-Disthe ratioof lowlevel duration tohorizontal period.
IfH-driveis takenonPin21 (Pin20 grounded), H-Disthe ratioof high level durationto horizontal period. both cases, H-D period driving horizontal scanning transistoroff.
9105-06.TBL
TDA9105
6/32
VERTICALSECTION
Operating Conditions
Symbol Parameter Min. Typ. Max. Unit
VSVR Vertical Sync Input Voltage (Pin 34) 0 5.5 V
VEWM Maximum EW Output Voltage (Pin 37) 6.5 V
VDHPCM Maximum Dynamic Horizontal Phase Control Output Voltage (Pin40) 6.5 V
VDHPCm Minimum Dynamic Horizontal Phase Control Output Voltage (Pin 40) 0.9 V
VDFm Minimum Vertical Dynamic Focus Output Voltage (Pin1) 0.9 V
Rload Minimum Loadfor less than 1% Vertical Amplitude Drift (Pin 25) 65 MΩ
9105-07.TBL
Electrical Characteristics (VCC= 12V, Tamb =25°C)
Symbol Parameter Test Conditions Min. Typ. Max. Unit
IBIASP Bias Current (current sourcedby PNP Base)
(Pins 28-29)
For V28-29 =2V 2 μA
IBIASN Bias Current (Pin 31) (sinkedby NPN base) For V31=6V 0.5 μA
VSth Vertical Sync Input Threshold Voltage (Pin 34) High-level
Low-level
VSBI Vertical Sync Input Bias Current
(Current Sourcedby PNP Base)
V34= 0.8V 1 μA
VRB Voltageat Ramp Bottom Point (Pin 27) 2/8 VREF-V
VRT Voltageat Ramp Top Point (with Sync) (Pin 27) 5/8 VREF-V
VRTF Voltageat Ramp Top Point (without Sync) (Pin
27)
VRT-0.1 V
VSW Minimum Vertical Sync Pulse Width (Pin34) 5 μS
VSmDut Vertical Sync Input Maximum Duty-cycle
(Pin 34) %
VSTD Vertical Sawtooth Discharge Time Duration
(Pin 27)
With 150nF cap 70 μS
VFRF Vertical Free Running Frequency V28= 2V,V29 grounded,
Measuredon Pin27
Cosc (Pin27)= 150nF
100 Hz
ASFR AUTO-SYNC Frequency (see Note1) With C27= 150nF 50 165 Hz
RAFD Ramp Amplitude Drift Versus Frequency V31= 6V, C27= 150nF
50Hz100 ppm/Hz
Rlin Ramp Linearityon Pin30 V28,V29 grounded 0.5 %
Vpos Vertical Position Adjustment Voltage (Pin32) V33 =2V
V33 =4V
V33=6V 3.65
3.3 V
IVPOS Max Currenton Vertical Position Control
Output (Pin 32)
±2mA
VOR Vertical Output Voltage (Pin30)
(peak-to-peak voltageon Pin30)
V31 =2V
V31 =4V
V31=6V 3.75
2.2 V
VOUTDC DC Voltageon Vertical Output (Pin30) See Note2 7/16 VREF-V
V0I Vertical Output Maximum Current(Pin 30) ±5mA
dVS Max Vertical S-Correction Amplitude
V28=2V inhibits S-CORR
V28=6V gives maximum S-CORR
ΔV/V30ppat T/4
ΔV/V30ppat 3T/4 TBD
TBD %
Ccorr Max Vertical C-Correction Amplitude V29 =2V
V29 =4V
V29=6V TBD
TBD %
VFlyTh Vertical Flyback Threshold (Pin 36) 1 TBD V
VFly Inh Inhibitionof VerticalFlyback Input (Pin36) See Note1 VREF- 0.5 V
IBIAS DCIN Bias Current (Pin 35) (sourcedby PNP base) For V35 =V32 2 μA
Notes:1.Itisthe frequency rangefor whichthe VERTICAL OSCILLATORwill automatically synchronize, using asinglecapacitor valueon
Pin27and witha constantramp amplitude. Typically 3.5Vfor Vertical reference voltage typical value (8V).
9105-08.TBL
TDA9105
7/32
VERTICAL SECTION (continued)
East/West Function
Symbol Parameter Test conditions Min. Typ. Max. Unit
EWDC DC Output Voltage (see Figure2) V33 =4V, V35 =V32,V38=4V 2.5 V
TDEWDC DC Output Voltage Thermal Drift See Note2 100 ppm/°C
EWpara Parabola Amplitude V28= 2V, V29 grounded,
V31= 6V, V33= 4V,
V35 =V32,V38= 4V,
V39 =6V
V39 =2V
TBD 2.9
EWtrack Parabola Amplitude versus V-AMP
Control (tracking between V-AMP and
E/W)
V28= 2V, V29 grounded
V33= 4V, V35 =V32,
V38= 4V, V39 =4V
V31 =2V
V31 =4V
V31 =6V
KeyAdj Keystone Adjustment Capability:
A/B Ratio (see Figure2)
B/A Ratio
V28= 2V, V29 grounded,
V31= 6V, V33= 4V,
V35 =V32,V39 =4V
V38 =6V
V38 =2V
TBD
TBD
Keytrack Keystone versusV-POS control
(tracking between V-POS and EW)
A/B Ratio
B/A Ratio
V28= 2V, V29 grounded,
V31= 6V, V38= 4V, V39 =6V
V33= 2V, V35 =V32
V33= 6V, V35 =V32
Notes:1. When Pin36 >VREF -0.5V,Vfly inputis inhibitedand vertical blankingon composite blankingoutputis replaced byvertical sawtooth
discharge time. These parametersarenot testedon each unit. Theyare measured duringour internal qualification procedure which includes
characterizationon batches comming from cornersofour processesand also temperaturecharacterization.
9105-09.TBL
Dynamic Horizontal Phase Control Function
Symbol Parameter Test Conditions Min. Typ. Max. Unit
DHPCDC DC Ouput Voltage (see Figure3) V33= 4V, V35 =V32,V41 =4V 4 V
TDDHPCDC DC Output Voltage Thermal Drift See Note 100 ppm/°C
SPBpara Side Pin BalanceParabola
Amplitude (see Figure3)
V28= 2V, V29 grounded,
V31= 6V, V33= 4V,
V35 =V32,V41 =4V
V42 =6V
V42 =2V
TBD +1.45 1.45 TBD
SPBtrack Side Pin balance Parabola
Amplitude versus V-amp Control
(tracking between V-amp and SPB)
V28= 2V, V29 grounded,
V33= 4V, V35 =V32,
V41= 4V, V42 =6V
V31 =2V
V31 =4V
V31 =6V
ParAdj Parallelogram Adjustment Capability
A/B ratio (see Figure.3)
B/A ratio
V28= 2V, V29 grounded,
V31= 6V, V33= 4V,
V35 =V32,V42 =6V
V41 =6V
V41 =2V
TBD
TBD
Partrack Parallelogram versus V-pos Control
(tracking between V-pos and DHPC)
A/B ratio
B/A ratio
V28= 2V, V29 grounded,
V31= 6V, V41= 4V, V42 =6V
V33= 2V, V35 =V32,
V33= 6V, V35 =V32
9105-10.TBL
TDA9105
8/32
VERTICAL SECTION (continued)
VerticalDynamic Focus Function
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VDFDC DC Output Voltage (see Figure4) V33= 4V, V35 =V32 6V
TDVDFDC DC Output Voltage Thermal Drift See Note 100 ppm/C
VDFAMP Parabola Amplitude versus V-amp
(tracking between V-amp and VDF)
(see Figure4)
V28= 2V, V29 grounded,
V33= 4V, V35 =V32,
V31 =2V
V31 =4V
V31 =6V
VDFKEY Parabola Assymetry versus V-pos
Control (tracking between V-pos
and VDF)
A/B ratio
B/A ratio
V28= 2V, V29 grounded,
V31= 6V,
V33= 2V, V35 =V32,
V33= 6V, V35 =V32
Note: These parametersarenot testedon each unit. They are measured duringour internal qualification procedure which includes
characterizationon batches comming from corners ofour processes andalso temperature characterization.
9105-11.TBL
TDA9105
9/32
PHASE
FREQUENCY
COMP
VCO
PHASE
COMP
PHASE
SHIFTER
LOCK
UNLOCK
IDENT
PULSE
SHAPER
SAFETY
PROCESSOR
PULSE
SHAPER
POL
DETECT 14 6
V-REF
PLL1
INHIB
CORR
PULSE
SHAPER
POL
DETECT26
V-REF
VERT
OSC
RAMP
GENERATOR
V-MID 424137 3938
BLK
GEN
H-FLY
V-SYNC
TDA9105
VIDEO
UNLOCK
220nF
10k
10k
10k
10k
470nF1%
150nF
12V
OUTPUT
BUFFER
MOIRE
H-SyncV-Sync
9105-03.EPS
Figure1: Testing Circuit
TDA9105
10/32
EWDC
EWPARA
9105-04.EPS
Figure2: E/W Output
DHPCDC
SPBPARA
V41 =6V
V42 =6V
V42 =2V
9105-05.EPS
Figure3: Dynamic Horizontal Phase Control
Output
VDFDCVDFAMP
V33 =2V
9105-06.EPS
Figure4: Vertical Dynamic Focus Function
TDA9105
11/32
TYPICAL VERTICAL OUTPUT WAVEFORMS
Function Control
Pin
Output
Pin
Control
Voltage Specification Picture Image
Vertical Size 31 30
Vertical
Position
Control 32
3.2V
3.5V
3.8V
Vertical
In/Out
This terminal isa Pin
controlling the center position geometric correction
signals. When connectedto
Pin32, ”Autotracking” occurs.
Vertical
Linearity 30
Vertical
Linearity 30
9105-13.TBL
9105-07.EPS
9105-13.EPS
VPP
VPP =4%
VPP
VPP =5%
VPP ΔV
VPP =5%
TDA9105
12/32
TYPICAL GEOMETRY OUTPUT WAVEFORMS
Function Control
Pin
Output
Pin
Control
Voltage Specification Picture Image
Trapezoid
Control 38 37
V39 =4V
Pin Cushion
Control 39 37
V38 =4V
Parrallelogram
Control 41 40
V42=4V
Side Pin
Balance
Control 40
V41 =4V
Vertical
Dynamic
Focus
Note: The specificationof Output voltageis indicatedon 4VPP vertical sawtooth output condition.The output voltage dependson vertical
sawtooth outputvoltage.
9105-14.TBL
/9105-14.EPS
9105-22.EPS
4.95V
2.95V
2.5V
4.95V
2.95V
2.5V
2.9V
2.5V4V4V
1.45V
1.45V
TDA9105
13/32
OPERATING DESCRIPTION
GENERAL CONSIDERATIONS
Power Supply
The typical valueof the power supply voltage VCC 12V. Perfect operationis obtainedif VCC ismain-
tainedin the limits: 10.8V→ 13.2V. orderto avoid erratic operationof the circuit
during the transient phaseof VCC switching on,or
switching off, the valueof VCC ismonitoredand the
outputsof the circuit are inhibitedif VCC< 7.6 typi-
cally. ordertohaveavery good powersupplyrejection,
the circuitis internally poweredby several internal
voltage references (The unique typical valueof
whichis 8V). Twoof these voltage references are
externally accessible, one for the vertical part and
one for the horizontal part. These voltage refer-
ences can be used for the DC control voltages
appliedon the concerned pinsby the wayof poten-
tiometersor digitalto analog converters (DAC’s).
Furthermoreit isnecessaryto filterthe a.m. voltage
referencesby the useof external capacitor con-
nectedto ground,in orderto minimize the noise
and consequently the ”jitter”on vertical and hori-
zontal output signals. Control Adjustments
The circuithas 10adjustmentcapabilities:2 forthe
horizontal part,2 for the E/W correction,4 for the
vertical part,2 for the Dynamic Horizontal phase
control.
The corresponding inputsof the circuit hasto be
driven witha DC voltage typically comprised be-
tween2 and 6V fora valueof the internal voltage
referenceof 8V.
PWM
DAC
Output
DCControl
Voltage
VREF
9105-23.EPS
Figure5: Exampleof Practical DC Control
Voltage Generation
9105-25.EPS
Figure7
H-SYNC 1.6V
9105-24.EPS
Figure6: Input Structure orderto havea good tracking with the voltage
reference value, it’s betterto maintain the control
voltages between VREF/4 and 3/4⋅ VREF.
The input currentof the DC control inputsis typi-
cally very low (abouta few μA). Dependingon the
internal structureof the inputs,it canbe positiveor
negative(sinkor source).
HORIZONTAL PART
Input section
The horizontal inputis designedto be sensitiveto
TTL signals typically comprised between0 and 5V.
Thetypical thresholdof this inputis 1.6V. This input
stage usesan NPN differentialstage and the input
currentis very low.
Concerning the duty cycleof the input signal, the
following signals maybe appliedto the circuit.
Using internal integration, both signals are recog-
nizedon conditionthat Z/T≤ 25%. Synchronisation
occurs on the leading edgeof the internal sync
signal. The minimum valueofZis 0.7μs.
PLL1
The PLL1is composedofa phase comparator,an
external filter anda Voltage Controlled Oscillator
(VCO).
Thephasecomparatoris a”phase frequency” type,
designedin CMOS technology. This kindof phase
detector avoids lockingon false frequencies.Itis
followedbya ”charge pump”, composedof2 cur-
rent sources sink and source(I =1mA typ.)
TDA9105
14/32
OPERATING DESCRIPTION (continued)
LOCKDET
H-LOCKOUT
H-LOCKCAP
COMP1INPUT
INTERFACE17H-SYNC
High
CHARGE
PUMP
Low
PLL
INHIBITION VCO
PLL1INHIB 11 10
PLL1F R0 C0
PHASE
ADJUST
H-POS
3.2V
OSC
9105-26.EPS
Figure8: Principle Diagram
The dynamic behaviourof the PLLis fixedby an
external filter which integrates the currentof the
charge pump.A ”CRC” filteris generally used (see
Figure 9).
PLL1is inhibitedby applyinga high levelon Pin14
(PLLinhib) whichisa TTLcompatible input. The inhibi-
tion results from the openingofa switch located be-
tween thechargepump andthe filter (see Figure8).
The VCO usesan external RC network.It delivers linear sawtooth obtained by charge and dis-
chargeof the capacitor,bya current proportionnal the currentin the resistor. typical thresholdsof
sawtooth are 1.6V and 6.4V (see Figure 10).
The control voltageof the VCOis typically com-
prised between 1.6V and 6V (see Figure 10). The
theoreticalfrequencyrangeof this VCOis intheratio → 3.75, but dueto spread and thermal driftof
externalcomponents and the circuit itself, the effec-
PLL1F
9105-27.EPS
Figure9
tive frequency range hastobe smaller (e.g. 30kHz 85kHz).In theabsenceof synchronisationsignal
the control voltageis equalto 1.6Vtyp. and theVCO
oscillatesonits lowest frequency (free frequency).
The synchro frequencyhastobealwayshigherthan
the free frequencyanda margin hastobe taken.As example fora synchro range from 30kHzto
85kHz, the suggestedfree frequencyis 27kHz.Loop
Filter
1.6V
6.4V
6.4V
1.6V 0.75TTFLIP FLOP
(1.6V4I0
9105-28.EPS
Figure10: Detailsof VCO
TDA9105
15/32
OPERATING DESCRIPTION (continued)
The PLL1 ensures the coincidence between the
leading edgeof the synchro signal anda phase
reference obtained by comparison between the
sawtoothof the VCO andan internal DC voltage
adjustable between 2.4V and 4V (byPin 15). Soa
±45°phase adjustmentis possible (see Figure 11).
20kΩ
220nF
From
Phase
Comparator
NOR1 A
6.5V
H-Lock CAP
HLOCKOUT
9105-30.EPS
Figure12: LOCK/UNLOCK Block Diagram Osc
Sawtooth
Phase REF1 Synchro
1.6V
6.4V
2.4V0.75T 0.25T
Phase REF1isobtainedby comparisonbetween thesawtoothand DCvoltage adjustable between 2.4Vand 4V.The PLL1ensures
the exact coincidence betweenthe signals phase REF and
HSYNS.A±T/8 phase adjustmentis possible.
9105-29.EPS
Figure11: PLL1 Timing Diagram
The twoVCO threshold canbe filteredby connect-
ing capacitoron Pins8-9.
The TDA9103 also includesa LOCK/UNLOCK
identification block which sensesin real-time
whether the PLLis lockedon the incominghorizon-
tal sync signalor not. The resulting informationis
availableon HLOCKOUToutput (Pin 2).The block
diagramof the LOCK/UNLOCK functionis de-
scribedin Figure 12.
The NOR1 gateis receiving the phase comparator
output pulses (which also drive the charge pump).
When the PLLis locked,on pointA thereisa very
small negative pulse (100ns)at each horizontal
cycle,so after R-C filter, thereisa high level on
Pin13 which force HLOCKOUTto high level (pro-
vided that HLOCKOUTis pulledupto VCC).
When the PLLis unlocked, the 100ns negative
pulse onA becomes muchlargerand consequently
the average levelon Pin13 will decrease. Whenit
reaches 6.5V, pointB goesto low level forcing
HLOCKOUT outputto ”0”.
The statusof Pin13is approximately thefollowing: Near 0V when thereisno H-SYNC, Between0 and4V with H-SYNC frequencydiffer-
ent from VCO, Between4 and 8V when H-SYNC frequency VCO frequency but notin phase, Nearto 8V when PLLis locked.is importantto notice that Pin13is notan output
pinand must onlybe usedfor filtering purpose (see
Figure 12).
TDA9105
16/32
